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CYM1836PZ-45C Datasheet(PDF) 1 Page - Cypress Semiconductor

Part # CYM1836PZ-45C
Description  128K x 32 Static RAM Module
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CYM1836PZ-45C Datasheet(HTML) 1 Page - Cypress Semiconductor

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128K x 32 Static RAM Module
CYM1836
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
February 15, 1999
Features
• High-density 4-megabit SRAM module
• 32-bit standard footprint supports densities from 16K
x 32 through 1M x 32
• High-speed CMOS SRAMs
— Access time of 15 ns
• Low active power
— 2.6W (max.) at 20 ns
• SMD technology
• TTL-compatible inputs and outputs
• Low profile
— Max. height of 0.57 in.
• Small PCB footprint
— 0.78 sq. in.
• Available in SIMM, ZIP format. SIMM suitable for vertical
or angled sockets.
Functional Description
The CYM1836 is a high-performance 4-megabit static RAM
module organized as 128K words by 32 bits. This module is
constructed from four 128K x 8 SRAMs in SOJ packages
mounted on an epoxy laminate board with pins. Four chip se-
lects (CS1, CS2, CS3, CS4) are used to independently enable
the four bytes. Reading or writing can be executed on individ-
ual bytes or any combination of multiple bytes through proper
use of selects.
Writing to each byte is accomplished when the appropriate
Chip Select (CS) and Write Enable (WE) inputs are both
LOW. Data on the input/output pins (I/O) is written into the
memory location specified on the address pins (A0 through
A16).
Reading the device is accomplished by taking the Chip Select
(CS) LOW while Write Enable (WE) remains HIGH. Under
these conditions, the contents of the memory location
specified on the address pins will appear on the data in-
put/output pins (I/O).
The data input/output pins stay at the high-impedance state
when write enable is LOW or the appropriate chip selects are
HIGH.
Two pins (PD0 and PD1) are used to identify module mem-
ory density in applications where alternate versions of the
JEDEC-standard modules can be interchanged.
Logic Block Diagram
Pin Configuration
1836–1
A0 − A16
OE
CS3
I/O0 − I/O7
ZIP/SIMM
Top View
CS1
CS2
CS4
I/O8 − I/O15
I/O16 − I/O23
I/O24 − I/O31
17
128K x 8
SRAM
4
SRAM
4
SRAM
4
SRAM
4
PD0−OPEN
PD1−OPEN
128K x 8
128K x 8
128K x 8
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
PD0
I/O0
I/O1
I/O2
I/O3
VCC
A7
A8
A9
I/O4
I/O5
I/O6
I/O7
GND
PD1
I/O8
I/O9
I/O10
I/O11
A0
A1
A2
I/O12
I/O13
I/O14
I/O15
GND
A15
CS2
CS4
NC
OE
I/O24
I/O25
I/O26
I/O27
A3
A4
A5
VCC
A6
I/O28
I/O29
I/O30
I/O31
WE
A14
CS1
CS3
A16
GND
I/O16
I/O17
I/O18
I/O19
A10
A11
A12
A13
I/O20
I/O21
I/O22
I/O23
GND
1836–2
WE


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