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MSM7603B Datasheet(PDF) 5 Page - OKI electronic componets |
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MSM7603B Datasheet(HTML) 5 Page - OKI electronic componets |
5 / 20 page ¡ Semiconductor MSM7603/7603B 5/20 PIN DESCRIPTIONS (Continued) Pin Symbol Type Description 8 RST I 9 PWDWN I 10 HD I 12 CLKIN I 16 SYNCO O This is the input pin for the reset signal. "L": Reset mode "H": Normal operation mode Due to initialization, input signals are disabled for 100 ms after reset (after RST is returned from "L" to "H"). Input the basic clock during the reset. Output pins during the reset are in the following sates : High impedance: SOUT, ROUT Not affected: SYNCO, SCKO This is the power-down mode control pin for power down operation "L": Power-down mode "H": Normal operation mode During power-down mode, all input pins are disabled and output pins are in the following states : High impedance : SOUT, ROUT "L": SYNCO, SCKO Reset after the power-down mode is released. This pin controls the howling detect function that detects and cancels a howling generated during hands-free talking for acoustic system. This function is used to cancel acoustic echoes. "L": Howling detector ON "H": Howling detector OFF This is the input pin for external input for the basic clock. Input the basic clock (17.5 to 20 MHz). When the internal sync signal (SYNCO, SCKO) is used, input the basic clock of 19.2 MHz. This is the output pin for the 8 kHz sync signal for the PCM codec. Connect to the SYNC pin and the PCMcodec transmit/receive sync pin. Leave open if using an external SYNC. 11 (m/A) I Used for MSM7603B only. This is the input pin for m-law PCM/A-law PCM interface select signal. "L": A-law PCM interface "H": m-law PCM interface For MSM7603, apply VDD. 13 VDD (PLL) I This is the power supply pin for the PLL circuit used for the basic clock. Insert a 0.1 mF capacitor with excellent high frequency characteristics between VDD (PLL) and VSS (PLL). 14 VSS (PLL) I This is the ground pin for the PLL circuit used for the basic clock. |
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