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LM5110-1MX Datasheet(PDF) 10 Page - National Semiconductor (TI) |
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LM5110-1MX Datasheet(HTML) 10 Page - National Semiconductor (TI) |
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10 / 13 page  Thermal Performance (Continued) The schematic above shows a conceptual diagram of the LM5110 output and MOSFET load. Q1 and Q2 are the switches within the gate driver. R G is the gate resistance of the external MOSFET, and C IN is the equivalent gate capaci- tance of the MOSFET. The gate resistance Rg is usually very small and losses in it can be neglected. The equivalent gate capacitance is a difficult parameter to measure since it is the combination of C GS (gate to source capacitance) and CGD (gate to drain capacitance). Both of these MOSFET capaci- tances are not constants and vary with the gate and drain voltage. The better way of quantifying gate capacitance is the total gate charge Q G in coloumbs. QG combines the charge required by C GS and CGD for a given gate drive voltage V GATE. Assuming negligible gate resistance, the total power dissi- pated in the MOSFET driver due to gate charge is approxi- mated by P DRIVER =VGATE xQG xFSW Where F SW = switching frequency of the MOSFET. As an example, consider the MOSFET MTD6N15 whose gate charge specified as 30 nC for V GATE = 12V. The power dissipation in the driver due to charging and discharging of MOSFET gate capacitances at switching fre- quency of 300 kHz and V GATE of 12V is equal to P DRIVER = 12V x 30 nC x 300 kHz = 0.108W. If both channels of the LM5110 are operating at equal fre- quency with equivalent loads, the total losses will be twice as this value which is 0.216W. In addition to the above gate charge power dissipation, - transient power is dissipated in the driver during output transitions. When either output of the LM5110 changes state, current will flow from V CC to VEE for a very brief interval of time through the output totem-pole N and P channel MOSFETs. The final component of power dissipation in the driver is the power associated with the quiescent bias cur- rent consumed by the driver input stage and Under-voltage lockout sections. Characterization of the LM5110 provides accurate estimates of the transient and quiescent power dissipation compo- nents. At 300 kHz switching frequency and 30 nC load used in the example, the transient power will be 8 mW. The 1 mA nominal quiescent current and 12V V GATE supply produce a 12 mW typical quiescent power. Therefore the total power dissipation P D = 0.216 + 0.008 + 0.012 = 0.236W. We know that the junction temperature is given by T J =PD x θ JA +TA Or the rise in temperature is given by T RISE =TJ −TA =PD x θ JA For SOIC-8 package θ JA is estimated as 170˚C/W for the conditions of natural convection. Therefore T RISE is equal to T RISE = 0.236 x 170 = 40.1˚C For LLP-10 package, the integrated circuit die is attached to leadframe die pad which is soldered directly to the printed circuit board. This substantially decreases the junction to ambient thermal resistance ( θ JA). θ JA as low as 40˚C/W is achievable with the LLP10 package. The resulting T RISE for the dual driver example above is thereby reduced to just 9.5 degrees. CONTINUOUS CURRENT RATING OF LM5110 The LM5110 can deliver pulsed source/sink currents of 3A and 5A to capacitive loads. In applications requiring continu- ous load current (resistive or inductive loads), package power dissipation, limits the LM5110 current capability far below the 5A sink/3A source capability. Rated continuous current can be estimated both when sourcing current to or sinking current from the load. For example when sinking, the maximum sink current can be calculated as where R DS(on) is the on resistance of lower MOSFET in the output stage of LM5110. Consider T J(max) of 125˚C and θ JA of 170˚C/W for an SO-8 package under the condition of natural convection and no air flow. If the ambient temperature (T A) is 60˚C, and the RD- 20079207 FIGURE 2. www.national.com 10 |
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