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LM5026 Datasheet(PDF) 3 Page - National Semiconductor (TI) |
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LM5026 Datasheet(HTML) 3 Page - National Semiconductor (TI) |
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3 / 23 page  Pin Descriptions (Continued) PIN NAME DESCRIPTION APPLICATION INFORMATION 8 OUT_A Main Output Driver Output of the main switch PWM gate driver. Capable of 3A peak sink current. 9 OUT_B Active Clamp Output Driver Output of the active clamp switch gate driver. Capable of 0.5A peak source and sink current. 10 PGND Power Ground Connect directly to Analog Ground 11 AGND Analog Return Connect directly to Power Ground. 12 SS Soft-start An external capacitor and an internal 50 µA current source set the soft-start ramp. The SS current source is reduced to 1 µA following a restart event. The soft-stop discharge current is 50 µA. 13 COMP Input to the Pulse Width Modulator The external opto-coupler connected to the COMP pin sources current into an internal NPN current mirror. The PWM duty cycle is maximum with zero input current, while 1mA reduces the duty cycle to zero. The current mirror improves the frequency response by reducing the ac voltage across the opto-coupler detector. 14 RT Oscillator Frequency Control Normally biased at 2V. The total external resistance connected between RT and AGND sets the internal oscillator frequency. 15 SYNC Oscillator Synchronization Input/Output The internal oscillator can be synchronized to an external clock with an external pull-down device. Multiple LM5026 devices can be synchronized together by connection of their SYNC pins. 16 DCL Maximum Duty Cycle Control An external resistor divider connected from RT to AGND sets the maximum output duty cycle for OUT_A. - Exposed Pad (LLP Package Only) Exposed Pad, underside of LLP package Connect to system ground plane for reduced thermal resistance. www.national.com 3 |
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