EP7211-CV-A datasheet(10/166 Pages) CIRRUS

Part #	EP7211-CV-A

Description	HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER

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Manufacturer	CIRRUS [Cirrus Logic]

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10 / 166 page

EP7211

High-Performance Ultra-Low-Power System-on-Chip with LCD Controller

10

DS352PP3

JUL 2001

LIST OF FIGURES

Figure 1-1.

A EP7211–Based System................................................................................................................... 3

Figure 2-1.

208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram ...............................................................13

Figure 2-2.

256-Ball Plastic Ball Grid Array Diagram .......................................................................................... 14

Figure 3-1.

EP7211 Block Diagram ..................................................................................................................... 37

Figure 3-2.

Codec Interrupt Timing ..................................................................................................................... 52

Figure 3-3.

Data Format of MCP Subframe 0 ..................................................................................................... 55

Figure 3-4.

MCP Packet Organization ................................................................................................................ 55

Figure 3-5.

Audio Codec Enable Timing ............................................................................................................. 57

Figure 3-6.

Format for the Audio and Telecom FIFOs.........................................................................................59

Figure 3-7.

SSI2 Port Directions in Slave and Master Mode............................................................................... 61

Figure 3-8.

Residual Byte Reading ..................................................................................................................... 63

Figure 3-9.

Video Buffer Mapping ....................................................................................................................... 66

Figure 3-10. State Diagram ................................................................................................................................... 72

Figure 3-11.

CLKEN Timing Entering the Standby State....................................................................................... 74

Figure 3-12.

CLKEN Timing Leaving the Standby State ...................................................................................... 75

Figure 3-13. A Maximum EP7211 Based System ................................................................................................. 77

Figure 5-1.

MCP Data Register 0: MCDR0 ....................................................................................................... 122

Figure 5-2.

MCP Data Register 1: MCDR1 ....................................................................................................... 124

Figure 5-3.

MCP Data Register 2: MCDR2 ....................................................................................................... 126

Figure 5-4.

MCP Status Register: MCSR ......................................................................................................... 131

Figure 6-1.

Expansion and ROM Timing ........................................................................................................... 137

Figure 6-2.

Expansion and ROM Sequential Read Timings.............................................................................. 138

Figure 6-3.

Expansion and ROM Write Timings ................................................................................................ 139

Figure 6-4.

DRAM Read Cycles at 13 MHz and 18.432 MHz ........................................................................... 140

Figure 6-5.

DRAM Read Cycles at 36 MHz ...................................................................................................... 141

Figure 6-6.

DRAM Write Cycles at 13 MHz and 18 MHz .................................................................................. 142

Figure 6-7.

DRAM Write Cycles at 36 MHz....................................................................................................... 143

Figure 6-8.

Video Quad Word Read from DRAM at 13 MHz and 18 MHz ........................................................ 144

Figure 6-9.

Quad Word Read from DRAM at 36 MHz.......................................................................................145

Figure 6-10. DRAM CAS Before RAS Refresh Cycle at 13 MHz and 18 MHz.................................................... 146

Figure 6-11.

DRAM CAS Before RAS Refresh Cycle at 36 MHz ........................................................................ 147

Figure 6-12. LCD Controller Timings................................................................................................................... 148

Figure 6-13. SSI Interface for AD7811/2 ............................................................................................................. 148

Figure 6-14. SSI Timing Interface for MAX148/9 ................................................................................................ 149

Figure 6-15. SSI2 Interface Timings.................................................................................................................... 149

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