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HY57V281620ETP-H Datasheet(PDF) 5 Page - Hynix Semiconductor |
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HY57V281620ETP-H Datasheet(HTML) 5 Page - Hynix Semiconductor |
5 / 13 page Rev. 1.1 / Jan. 2005 5 Synchronous DRAM Memory 128Mbit (8Mx16bit) HY57V281620E(L)T(P) Series FUNCTIONAL BLOCK DIAGRAM 2Mbit x 4banks x 16 I/O Synchronous DRAM Internal Row Counter Column Pre Decoder Column Add Counter Self refresh logic & timer Address Register Burst Counter Mode Register Bank Select Column Active Row Active CAS Latency CLK CKE CS RAS CAS WE U/LDQM A0 A1 BA1 BA0 A11 Row Pre Decoder Refresh DQ0 DQ15 Y-Decoder 2Mx16 BANK 0 2Mx16 BANK 1 2Mx16 BANK 2 2Mx16 BANK 3 Memory Cell Array Data Out Control Pipe Line Control |
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