CY7C1062AV33
Document #: 38-05137 Rev. *D
Page 4 of 9
AC Switching Characteristics Over the Operating Range[4]
Parameter
Description
–8
–10
–12
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle
tpower
VCC (typical) to the first access
[5]
111
ms
tRC
Read Cycle Time
8
10
12
ns
tAA
Address to Data Valid
8
10
12
ns
tOHA
Data Hold from Address Change
3
3
3
ns
tACE
CE1, CE2, or CE3 LOW to Data Valid
8
10
12
ns
tDOE
OE LOW to Data Valid
5
5
6
ns
tLZOE
OE LOW to Low-Z[6]
111
ns
tHZOE
OE HIGH to High-Z[6]
556
ns
tLZCE
CE1, CE2, or CE3 LOW to Low-Z
[6]
333
ns
tHZCE
CE1, CE2, or CE3 HIGH to High-Z
[6]
556
ns
tPU
CE1, CE2, or CE3 LOW to Power-up
[7]
000
ns
tPD
CE1, CE2, or CE3 HIGH to Power-down
[7]
810
12
ns
tDBE
Byte Enable to Data Valid
5
5
6
ns
tLZBE
Byte Enable to Low-Z[6]
111
ns
tHZBE
Byte Disable to High-Z[6]
556
ns
Write Cycle[8, 9]
tWC
Write Cycle Time
8
10
12
ns
tSCE
CE1, CE2, or CE3 LOW to Write End
6
7
8
ns
tAW
Address Set-up to Write End
6
7
8
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
678
ns
tSD
Data Set-up to Write End
5
5.5
6
ns
tHD
Data Hold from Write End
0
0
0
ns
tLZWE
WE HIGH to Low-Z[6]
333
ns
tHZWE
WE LOW to High-Z[6]
556
ns
tBW
Byte Enable to End of Write
6
7
8
ns
Notes:
4.
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and transmission line loads. Test conditions for the read cycle use output loading as shown in (a) of AC Test Loads, unless specified otherwise.
5.
This part has a voltage regulator that steps down the voltage from 3V to 2V internally. tpower time has to be provided initially before a read/write operation is started.
6.
tHZOE, tHZCE, tHZWE, tHZBE, and tLZOE, tLZCE, tLZWE, and tLZBE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured
± 200 mV from steady-state voltage.
7.
These parameters are guaranteed by design and are not tested.
8.
The internal write time of the memory is defined by the overlap of CE1 LOW, CE 2 HIGH, CE3 LOW, and WE LOW. The chip enables must be active and WE
must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced
to the leading edge of the signal that terminates the write.
9.
The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
3.0V
3.0V
tCDR
VDR > 2V
DATA RETENTION MODE
tR
CE
VCC
Data Retention Waveform
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