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PI6C3Q991-5IJ Datasheet(PDF) 8 Page - Pericom Semiconductor Corporation |
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PI6C3Q991-5IJ Datasheet(HTML) 8 Page - Pericom Semiconductor Corporation |
8 / 10 page 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI6C3Q991, PI6CQ3993 3.3V Programmable Skew PLL Clock Driver SuperClock® 8 PS8449A 10/09/00 tREF tRPWH tODCV tSKEWPR tSKEW0, 1 tSKEW3,4 tSKEW3,4 tSKEW3,4 tSKEW2,4 tSKEW1,3,4 tSKEWPR tSKEW0, 1 tPD tODCV tRPWL tJR REF FB Q Other Q Inverted Q REF Divided by 2 REF Divided by 4 tSKEW2 tSKEW2 l o b m y Sn o it p i r c s e D. n i M. x a Ms ti n U tR t , F V 0 . 2 o t V 8 . 0 ,s e m it ll a f d n a e si r t u p n i m u m i x a M0 1V / s n t C W P W O L r o H G I H , e sl u p k c o l c t u p n I3 s n DH el c y c y t u d t u p n I0 10 9% Table12.InputTimingRequirements Notes: 1. Input timing requirements are guaranteed by design but not tested. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies. ACTimingDiagram Notes: VCCQ/PE: The AC timing diagram above applies to VCCQ/PE=VCC. For VCCQ/PE=GND, the negative edge of FB aligns with the negative edge of REF, divided outputs change on the negative edge of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align. Skew: The time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 20pF and terminated with 75Ohm to VCC/2. tSKEWPR: The skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU. tSKEW0: The skew between outputs when they are selected for 0t U. tDEV: The output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow, etc.) tODCV: The deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications. tLOCK: The time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits. tPWH is measured at 2.0V. tPWL is measured at 0.8V. tORISE and tOFALL are measured between 0.8V and 2.0V. |
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