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July 2004
AS91L1006BU
Signal Description
PIN NAME
PIN
TYPE
PIN
NUMBER
LQFP
PIN
NUMBER
FPBGA
DESCRIPTION
Stable state
after port/reset
LSP1_TCK
OUT
31
H4
IEEE1149.1 Test Clock on LSP 1
when PASS_THRU_ENABLE is
HIGH.
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 000.
This pin is tri-stated for all other
combinations.
Buffered version
of signal present
on primary TCK
LSP1_TMS
OUT
32
J4
IEEE1149.1 Test Mode Select on
LSP 1 when PASS_THRU_ENABLE
is HIGH.
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 000.
This pin is tri-stated for all other
combinations.
Logic '1'
LSP1_TDO
OUT
35
H5
IEEE1149.1 Test Data Out on LSP 1
when PASS_THRU_ENABLE is
HIGH.
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 000.
This pin is tri-stated for all other
combinations.
Logic '1'
LSP1_TDI
IN
33
K4
IEEE1149.1 Test Data In on LSP 1
when PASS_THRU_ENABLE is
HIGH.
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 000.
LSP1_TRST
OUT
29
K3
IEEE1149.1 Test Reset on LSP 1
when PASS_THRU_ENABLE is
HIGH.
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 000.
This pin is tri-stated for all other
combinations.
Buffered version
of signal present
on primary TRST
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