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UPA1830GR-9JG Datasheet(PDF) 2 Page - NEC |
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UPA1830GR-9JG Datasheet(HTML) 2 Page - NEC |
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2 / 8 page  Data Sheet G16268EJ1V0DS 2 µµµµPA1830 ELECTRICAL CHARACTERISTICS (TA = 25°C) CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Zero Gate Voltage Drain Current IDSS VDS = −30 V, VGS = 0 V −1.0 µA Gate Leakage Current IGSS VGS = m20 V, VDS = 0 V m10 µA Gate Cut-off Voltage VGS(off) VDS = −10 V, ID = −1.0 mA −1.0 −2.0 −2.5 V Forward Transfer Admittance | yfs | VDS = −10 V, ID = −4.5 A 8.0 17.4 S Drain to Source On-state Resistance RDS(on)1 VGS = −10 V, ID = −4.5 A 13.7 17 m Ω RDS(on)2 VGS = −4.5 V, ID = −4.5 A 18.5 24.5 m Ω RDS(on)3 VGS = −4.0 V, ID = −4.5 A 21 28 m Ω Input Capacitance Ciss VDS = −10 V 1950 pF Output Capacitance Coss VGS = 0 V 570 pF Reverse Transfer Capacitance Crss f = 1.0 MHz 350 pF Turn-on Delay Time td(on) VDD = −15 V, ID = −4.5 A 17 ns Rise Time tr VGS = −10 V 16 ns Turn-off Delay Time td(off) RG = 10 Ω 140 ns Fall Time tf 150 ns Total Gate Charge QG VDD = −24 V 38 nC Gate to Source Charge QGS VGS = −10 V 4.5 nC Gate to Drain Charge QGD ID = −9.0 A 12 nC Body Diode Forward Voltage VF(S-D) IF = 9.0 A, VGS = 0 V 0.84 V Reverse Recovery Time trr IF = 9.0 A, VGS = 0 V 60 ns Reverse Recovery Charge Qrr di/dt = 100 A/ µs40 nC TEST CIRCUIT 2 GATE CHARGE TEST CIRCUIT 1 SWITCHING TIME PG. RG 0 VGS(−) D.U.T. RL VDD τ = 1 s µ Duty Cycle ≤ 1% τ PG. 50 Ω D.U.T. RL VDD IG = −2 mA VGS Wave Form VDS Wave Form VGS(−) VDS(−) 10% 0 0 90% 90% 90% VGS VDS ton toff td(on) tr td(off) tf 10% 10% |
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