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TPS3514DR Datasheet(PDF) 8 Page - Texas Instruments |
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TPS3514DR Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 16 page  TPS3514 SLVS422A – JULY 2003 www.ti.com 8 TYPICAL CHARACTERISTICS (Cont.) TA = 25° unless otherwise noted. DETAILED DESCRIPTION POWER-GOOD AND POWER-GOOD DELAY A PC power supply is commonly designed to provide a power-good signal, which is defined by the computer manufacturers. Power-Good Output (PGO) is a power-good indicator and should be asserted HIGH by the PC power supply to indicate that the 5VDC and 3.3VDC outputs are above the under-voltage threshold limit. At this time, the supply should be able to provide enough power to assure continuous operation within the specification. Conversely, when either the 5VDC or the 3.3VDC output voltages fall below the under-voltage threshold, or when main power has been removed for a sufficiently long time so that power-supply operation is no longer assured, PGO should be deasserted to a LOW state. The power-good, DC enable (PSON), and the 5V/3.3V supply rails are shown in Figure 1. Although there is no requirement to meet specific timing parameters, the following signal timings are recommended: 2ms ≤ t2 ≤ 20ms, 100ms < t3 < 2000ms, t4 > 1ms, t5 ≤ 10ms t2 t3 t5 t4 5V/3.3V Output PSON PGO On Off 75% 10% FIGURE 1: Timing of PSON and PGO. |
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