CY28405
Document #: 38-07512 Rev. *B
Page 6 of 19
Byte 2: Control Register 2
Bit
@Pup
Name
Description
7
0
Reserved
Reserved, set = 0
6
0
Reserved
Reserved, set = 0
5
0
CPUT_ITP, CPUC_ITP
CPUT/C_ITP Pwrdwn drive mode
0 = Driven in power- down, 1 = three-state
4
0
CPUT1, CPUC1
CPU(T/C)1 Pwrdwn drive mode
0 = Driven in power-down, 1 = three-state
3
0
CPUT0, CPUC0
CPU(T/C)0 Pwrdwn drive mode
0 = Driven in power-down, 1 = three-state
2
0
Reserved
Reserved
1
0
Reserved
Reserved
0
0
Reserved
Reserved
Byte 3: Control Register 3
Bit
@Pup
Name
Description
7
1
SW PCI_STP Function
0= PCI_STP assert, 1= PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI and PCIF outputs will be
stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI and PCIF outputs will resume
in a synchronous manner with no short pulses.
6
1
Reserved
Reserved
5
1
PCI5
PCI5 Output Enable
0 = Disabled, 1 = Enabled
4
1
PCI4
PCI4 Output Enable
0 = Disabled, 1 = Enabled
3
1
PCI3
PCI3 Output Enable
0 = Disabled, 1 = Enabled
2
1
PCI2
PCI2 Output Enable
0 = Disabled, 1 = Enabled
1
1
PCI1
PCI1 Output Enable
0 = Disabled, 1 = Enabled
0
1
PCI0
PCI0 Output Enable
0 = Disabled, 1 = Enabled
Byte 4: Control Register 4
Bit
@Pup
Name
Description
7
0
USB_48
USB 48 Drive Strength Control
0 = High Drive Strength, 1 = Low Drive Strength
6
1
USB_48
USB_48 Output Enable
0 = Disabled, 1 = Enabled
5
0
PCIF2
Allow control of PCIF2 with assertion of SW PCI_STP
0 = Free Running, 1 = Stopped with SW PCI_STP
4
0
PCIF1
Allow control of PCIF1 with assertion of SW PCI_STP
0 = Free Running, 1 = Stopped with SW PCI_STP
3
0
PCIF0
Allow control of PCIF0 with assertion of SW PCI_STP
0 = Free Running, 1 = Stopped with SW PCI_STP
2
1
PCIF2
PCIF2 Output Enable
0 = Disabled, 1 = Enabled
1
1
PCIF1
PCIF1 Output Enable
0 = Disabled, 1 = Enabled
0
1
PCIF0
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
