CY28405
Document #: 38-07512 Rev. *B
Page 5 of 19
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Byte Read Protocol
Bit
Description
Bit
Description
1Start
1Start
2:8
Slave address – 7 bits
2:8
Slave address – 7 bits
9
Write = 0
9
Write = 0
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code – 8 bits
‘1xxxxxxx’ stands for byte operation, bits[6:0] of
the command code represents the offset of the
byte to be accessed
11:18
Command Code – 8 bits
‘1xxxxxxx’ stands for byte operation, bits[6:0]
of the command code represents the offset of
the byte to be accessed
19
Acknowledge from slave
19
Acknowledge from slave
20:27
Data byte from master – 8 bits
20
Repeat start
28
Acknowledge from slave
21:27
Slave address – 7 bits
29
Stop
28
Read = 1
29
Acknowledge from slave
30:37
Data byte from slave – 8 bits
38
Not Acknowledge
39
Stop
Byte 0: Control Register 0
Bit
@Pup
Name
Description
7
0
Reserved, Set= 0
6
1
PCIF
PCI
PCI Drive Strength Override
0 = Force All PCI and PCIF Outputs to Low Drive Strength
1= Force All PCI and PCIF Outputs to High Drive Strength
5
0
Reserved
Reserved, Set= 0
4
HW
FS_E
Power up latched value of FS_E pin
3
HW
FS_D
Power up latched value of FS_D pin
2
HW
FS_C
Power up latched value of FS_C pin
1
HW
FS_B
Power up latched value of FS_B pin
0
HW
FS_A
Power up latched value of FS_A pin
Byte 1: Control Register 1
Bit
@Pup
Name
Description
7
0
Reserved
Reserved, set = 0
6
1
Reserved
Reserved, set = 1
5
1
Reserved
Reserved, set = 1
4
1
Reserved
Reserved, set = 1
3
1
Reserved
Reserved, set = 1
2
1
CPUT_ITP, CPUC_ITP
CPUT/C_ITP Output Enable
0 = Disabled (three-state), 1 = Enabled
1
1
CPUT1, CPUC1
CPU(T/C)1 Output Enable,
0 = Disabled (three-state), 1 = Enabled
0
1
CPUT0, CPUC0
CPU(T/C)0 Output Enable
0 = Disabled (three-state), 1 = Enabled
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