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AS7C34096-12JI Datasheet(PDF) 1 Page - Alliance Semiconductor Corporation |
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AS7C34096-12JI Datasheet(HTML) 1 Page - Alliance Semiconductor Corporation |
1 / 9 page January 2005 Copyright © Alliance Semiconductor. All rights reserved. AS7C4096 AS7C34096 5V/3.3V 512K × 8 CMOS SRAM ® 1/13/05; v.1.9 Alliance Semiconductor P. 1 of 9 Features • AS7C4096 (5V version) • AS7C34096 (3.3V version) • Industrial and commercial temperature • Organization: 524,288 words × 8 bits • Center power and ground pins • High speed - 10/12/15/20 ns address access time - 5/6/7/8 ns output enable access time • Low power consumption: ACTIVE - 1375 mW (AS7C4096) / max @ 12 ns - 576 mW (AS7C34096) / max @ 10 ns • Low power consumption: STANDBY - 110 mW (AS7C4096) / max CMOS - 72 mW (AS7C34096) / max CMOS • Equal access and cycle times • Easy memory expansion with CE, OE inputs • TTL-compatible, three-state I/O • JEDEC standard packages - 400 mil 36-pin SOJ - 44-pin TSOP 2 • ESD protection ≥ 2000 volts • Latch-up current ≥ 100 mA Logic block diagram 524,288 × 8 Array (4,194,304) Input buffer I/O8 I/O1 OE CE WE Column decoder Control Circuit A0 A1 A2 A3 A4 A5 A6 A7 VCC GND A8 A9 Pin arrangement s 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 A15 OE I/O8 I/O7 GND VCC I/O6 I/O5 A14 A13 A12 A11 A10 NC A0 A1 A2 A3 A4 CE I/O1 I/O2 VCC GND I/O3 I/O4 WE A5 A6 A7 17 18 A8 A9 36 35 34 33 NC A18 A17 A16 GND VCC I/O6 I/O5 NC A14 A13 A12 A11 A10 A4 CE I/O1 I/O2 VCC GND I/O3 I/O4 WE A5 A6 A7 A8 A9 I/O8 I/O7 A1 A2 A3 A0 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 43 42 41 44 A16 A15 A17 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 2 3 4 1 NC NC NC NC NC NC NC NC NC OE A18 36-pin SOJ (400 mil) 44-pin TSOP 2 Selection guide –10 –12 –15 –20 Unit Maximum address access time 10 12 15 20 ns Maximum outputenable access time 5 6 7 8 ns Maximum operating current AS7C4096 – 250 220 180 mA AS7C34096 160 130 110 100 mA Maximum CMOS standby current AS7C4096 – 20 20 20 mA AS7C34096 20 20 20 20 mA |
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