K4J52324QC-BJ14 datasheet(4/57 Pages) SAMSUNG

Part #	K4J52324QC-BJ14

Description	512Mbit GDDR3 SDRAM

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Manufacturer	SAMSUNG [Samsung semiconductor]

Direct Link	http://www.samsung.com/Products/Semiconductor

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Rev 1.0 (Mar 2005)

512M GDDR3 SDRAM

K4J52324QC-B

• 2.0V + 0.1V power supply for device operation for -BJ**

• 2.0V + 0.1V power supply for I/O interface for -BJ**

• 1.8V + 0.1V power supply for device operation for -BC**

• 1.8V + 0.1V power supply for I/O interface for -BC**

• On-Die Termination (ODT)

• Output Driver Strength adjustment by EMRS

• Calibrated output drive

• 1.8V Pseudo Open drain compatible inputs/outputs

• 4 internal banks for concurrent operation

• Differential clock inputs (CK and CK)

• Commands entered on each positive CK edge

• CAS latency : 4, 5, 6, 7, 8, 9, 10, 11 (clock)

• Additive latency (AL): 0 and 1 (clock)

• Programmable Burst length : 4 and 8

• Programmable Write latency : 1, 2, 3, 4, 5, 6 and 7 (clock)

GENERAL DESCRIPTION

FEATURES

• Single ended READ strobe (RDQS) per byte

• Single ended WRITE strobe (WDQS) per byte

• RDQS edge-aligned with data for READs

• WDQS center-aligned with data for WRITEs

• Data Mask(DM) for masking WRITE data

• Auto & Self refresh modes

• Auto Precharge option

• 32ms, auto refresh (8K cycle)

• 136 Ball FBGA

• Maximum clock frequency up to 800MHz

• Maximum data rate up to 1.6Gbps/pin

• DLL for outputs

• Boundary scan function with SEN pin

• Mirror function with MF pin

2M x 32Bit x 8 Banks Graphic Double Data Rate 3 Synchronous DRAM

with Uni-directional Data Strobe

ORDERING INFORMATION

* K4J52324QC-A*** is leaded package part number

Part NO.

Max Freq.

Max Data Rate

VDD&VDDQ

Package

K4J52324QC-BJ12

800MHz

1.6Gbps/pin

2.0V+0.1V

136 Ball FBGA

K4J52324QC-BJ14

700MHz

1.4Gbps/pin

K4J52324QC-BC14

700MHz

1.4Gbps/pin

1.8V+0.1V

K4J52324QC-BC16

600MHz

1.2Gbps/pin

K4J52324QC-BC20

500MHz

1.0Gbps/pin

The K4J52324QC is 536,870,912 bits of hyper synchronous data rate Dynamic RAM organized as 8 x 2,097,152 words by

32 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous features with Data Strobe allow

extremely high performance up to 6.4GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of

operating frequencies, and programmable latencies allow the device to be useful for a variety of high performance memory

system applications.

FOR 2M x 32Bit x 8 Bank GDDR3 SDRAM

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K4J52324QC-BJ14 Datasheet(PDF) 4 Page - Samsung semiconductor

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