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AD5380EB Datasheet(PDF) 6 Page - Analog Devices |
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AD5380EB Datasheet(HTML) 6 Page - Analog Devices |
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6 / 34 page  PRELIMINARY TECHNICAL DATA REV. PrF 09/2003 –6– SERIAL INTERFACE Parameter 1,2,3 Limit at TMIN, TMAX Units Description t1 33 ns min SCLK Cycle Time t2 13 ns min SCLK High Time t3 13 ns min SCLK Low Time t4 13 ns min SYNC Falling Edge to SCLK Falling Edge Setup Time t5 4 13 ns min 24th SCLK Falling Edge to SYNC Falling Edge t6 4 33 ns min Minimum SYNC Low Time t7 10 ns min Minimum SYNC High Time t7A 50 ns min Minimum SYNC High Time in Readback Mode t8 5 ns min Data Setup Time t9 4.5 ns min Data Hold Time t10 4,5 30 ns max 24th SCLK Falling Edge to BUSY Falling Edge t11 900 ns typ BUSY Pulse Width Low (Single Channel Update) t12 4 20 ns min 24th SCLK Falling Edge to LDAC Falling Edge t13 20 ns min LDAC Pulse Width Low t14 100 ns max BUSY Rising Edge to DAC Output Response Time t15 0 ns min BUSY Rising Edge to LDAC Falling Edge t16 100 ns min LDAC Falling Edge to DAC Output Response Time t17 8 µs typ DAC Output Settling Time, Boost Mode off. t18 20 ns min CLR Pulse Width Low t19 12 µs max CLR Pulse Activation Time t20 6,7 20 ns max SCLK Rising Edge to SDO Valid t21 7 5 ns min SCLK Falling Edge to SYNC Rising Edge t22 7 8 ns min SYNC Rising Edge to SCLK Rising Edge t23 7 20 ns min SYNC Rising Edge to LDAC Falling Edge NOTES 1Guaranteed by design and characterization, not production tested. 2All input signals are specified with t r = tf = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.2 V. 3See Figures 3 and 4 4Stand-Alone Mode only. 5This is measured with the load circuit of Figure 1a. 6This is measured with the load circuit of Figure 1b. 7Daisy-Chain Mode only. Specifications subject to change without notice. (DVDD= 2.7V to 5.5V ; AVDD=+4.5V to +5.5V or +2.7V to +3.6V; AGND= DGND = 0 V; ) All specifications TMIN to TMAX unless otherwise noted.) TIMING CHARACTERISTICS I OL 200u A I OH 200u A C L 50pF TO OUT P UT PIN VOH (M IN) or VOL (MAX) CL 50pF RL 2.2k TO OUTPUT PIN VOL VCC Figure 1a Load Circuit for BUSY Timing Diagram Figure 1b. Load Circuit for SDO Timing Diagram (Serial Interface, Daisy-Chain mode) |
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