CY24142
Document #: 38-07532 Rev. *B
Page 3 of 7
Absolute Maximum Conditions
(Above which the useful life may be impaired. For user guide-
lines, not tested.
Supply Voltage (VDD, AVDD, VDDL) ...................–0.5 to +7.0V
DC Input Voltage...................................... –0.5V to VDD + 0.5
Storage Temperature (Non-Condensing).... –55
°C to +125°C
Junction Temperature ................................ –40
°C to +125°C
Data Retention @ Tj=125
°C..................................> 10 years
Package Power Dissipation...................................... 350 mW
ESD (Human Body Model) MIL-STD-883.................... 2000V
Recommended Crystal Specifications
Parameter
Description
Comments
Min.
Typ.
Max.
Unit
FNOM
Nominal crystal frequency
Parallel resonance, fundamental mode, AT cut
18.432
MHz
CLNOM
Nominal load capacitance
14
pF
R1
Equivalent series resistance
(ESR)
Fundamental mode
25
Ω
R3/R1
Ratio of third overtone mode ESR
to fundamental mode ESR
Ratio used because typical R1values are much
less than the maximum spec
3
DL
Crystal drive level
No external series resistor assumed
0.5
2
mW
Recommended Operating Conditions
Parameter
Description
Min.
Typ.
Max.
Unit
VDD, AVDD, VDDL Supply Voltage
3.15
3.45
3.6
V
TA
Ambient Temperature
0
85
°C
CLOAD
Max. Load Capacitance
15
pF
TPU
Power-up time for all VDDs to reach minimum specified voltage (power
ramps must be monotonic)
0.05
500
ms
DC Electrical Specifications
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
IOH[2]
Output High Current
VOH = VDD – 0.5, VDD/VDDL = 3.45V
12
24
mA
IOL[2]
Output Low Current
VOL = 0.5, VDD/VDDL = 3.45V
12
24
mA
IIH
Input High Current
VIH = VDD
50
µA
IIL
Input Low Current
VIL = 0V
5
10
µA
VIH
Input High Voltage
CMOS levels, 70% of VDD
0.7
VDD
VIL
Input Low Voltage
CMOS levels, 30% of VDD
0.3
VDD
IVDD
Supply Current
AVDD/VDD Current
25
mA
IVDDL
Supply Current
VDDL Current
20
mA
RDOWN
Pull-down resistor on Inputs
VDD = 3.15 to 3.6V, measured VIN = 3.45V
100
150
k
Ω
CXTAL[2]
Crystal Load Capacitance
Total effective load of internal load caps
12.9
pF
Cycle-Cycle Jitter Specifications (VDD = 3.15V – 3.6V)
Parameter
Description
Conditions
1
σ
Typ.
Max.
Unit
t9
Clock Jitter–peak-peak
Cycle-Cycle Jitter–18.432 MHz
20
120
200
ps
t9
Clock Jitter–peak-peak
Cycle-Cycle Jitter–54 MHz
40
150
250
ps
t9
Clock Jitter–peak-peak
Cycle-Cycle Jitter–13.5 MHz
20
120
200
ps
Note:
2. Guaranteed by characterization, not 100% tested.
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