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CDB42528 Datasheet(PDF) 4 Page - Cirrus Logic

Part # CDB42528
Description  114 dB, 192 kHz 8-Ch Codec with S/PDIF Receiver
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CDB42528 Datasheet(HTML) 4 Page - Cirrus Logic

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CS42528
4
DS586PP5
12. APPENDIX C: PLL FILTER .................................................................................................. 80
12.1 External Filter Components ........................................................................................... 81
12.1.1 General ............................................................................................................. 81
12.1.2 Jitter Attenuation ............................................................................................... 81
12.1.3 Capacitor Selection ........................................................................................... 82
12.1.4 Circuit Board Layout .......................................................................................... 82
13. APPENDIX D: EXTERNAL AES3/SPDIF/IEC60958 RECEIVER COMPONENTS .............. 83
13.1 AES3 Receiver External Components ........................................................................... 83
14. APPENDIX E: ADC FILTER PLOTS .................................................................................... 84
15. APPENDIX F: DAC FILTER PLOTS .................................................................................... 86
LIST OF FIGURES
Figure 1. Serial Audio Port Master Mode Timing .......................................................................... 12
Figure 2. Serial Audio Port Slave Mode Timing ............................................................................ 12
Figure 3. Control Port Timing - I2C Format ................................................................................... 13
Figure 4. Control Port Timing - SPI Format................................................................................... 14
Figure 5. Typical Connection Diagram .......................................................................................... 20
Figure 6. Full-Scale Analog Input .................................................................................................. 21
Figure 7. Full-Scale Output ........................................................................................................... 22
Figure 8. ATAPI Block Diagram (x = channel pair 1, 2, 3, 4)......................................................... 23
Figure 9. CS42528 Clock Generation ........................................................................................... 25
Figure 10. I2S Serial Audio Formats.............................................................................................. 29
Figure 11. Left Justified Serial Audio Formats .............................................................................. 30
Figure 12. Right Justified Serial Audio Formats ............................................................................ 30
Figure 13. One Line Mode #1 Serial Audio Format....................................................................... 31
Figure 14. One Line Mode #2 Serial Audio Format....................................................................... 31
Figure 15. ADCIN1/ADCIN2 Serial Audio Format ......................................................................... 32
Figure 16. OLM Configuration #1 .................................................................................................. 33
Figure 17. OLM Configuration #2 .................................................................................................. 34
Figure 18. OLM Configuration #3 .................................................................................................. 35
Figure 19. OLM Configuration #4 .................................................................................................. 36
Figure 20. OLM Configuration #5 .................................................................................................. 37
Figure 21. Control Port Timing in SPI Mode.................................................................................. 38
Figure 22. Control Port Timing, I2C Write...................................................................................... 39
Figure 23. Control Port Timing, I2C Read ..................................................................................... 39
Figure 24. Recommended Analog Input Buffer ............................................................................. 76
Figure 25. Recommended Analog Output Buffer .......................................................................... 76
Figure 26. Channel Status Data Buffer Structure.......................................................................... 78
Figure 27. PLL Block Diagram ...................................................................................................... 80
Figure 28. Jitter Attenuation Characteristics of PLL ...................................................................... 81
Figure 29. Recommended Layout Example .................................................................................. 82
Figure 30. Consumer Input Circuit ................................................................................................ 83
Figure 31. S/PDIF MUX Input Circuit ............................................................................................ 83
Figure 32. TTL/CMOS Input Circuit...............................................................................................83
Figure 33. Single Speed Mode Stopband Rejection ..................................................................... 84
Figure 34. Single Speed Mode Transition Band............................................................................ 84
Figure 35. Single Speed Mode Transition Band (Detail) ............................................................... 84
Figure 36. Single Speed Mode Passband Ripple.......................................................................... 84
Figure 37. Double Speed Mode Stopband Rejection .................................................................... 84
Figure 38. Double Speed Mode Transition Band .......................................................................... 84
Figure 39. Double Speed Mode Transition Band (Detail).............................................................. 85
Figure 40. Double Speed Mode Passband Ripple ........................................................................ 85
Figure 41. Quad Speed Mode Stopband Rejection....................................................................... 85


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