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DP83816AVNG Datasheet(PDF) 5 Page - National Semiconductor (TI) |
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DP83816AVNG Datasheet(HTML) 5 Page - National Semiconductor (TI) |
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5 / 105 page  5 www.national.com 2.0 Pin Description PCI Bus Interface Symbol LQFP Pin No(s) Dir Description AD[31-0] 66, 67, 68, 70, 71, 72, 73, 74, 78, 79, 81, 82, 83, 86, 87, 88, 101, 102, 104, 105, 106, 108, 109, 110, 112, 113, 115, 116, 118, 119, 120, 121 I/O Address and Data: Multiplexed address and data bus. As a bus master, the DP83816 will drive address during the first bus phase. During subsequent phases, the DP83816 will either read or write data expecting the target to increment its address pointer. As a bus target, the DP83816 will decode each address on the bus and respond if it is the target being addressed. CBEN[3-0] 75, 89, 100, 111 I/O Bus Command/Byte Enable: During the address phase these signals define the “bus command” or the type of bus transaction that will take place. During the data phase these pins indicate which byte lanes contain valid data. CBEN[0] applies to byte 0 (bits 7-0) and CBEN[3] applies to byte 3 (bits 31-24) in the Little Endian Mode. In Big Endian Mode, CBEN[3] applies to byte 0 (bits 31-24) and CBEN[0] applies to byte 3 (bits 7-0). PCICLK 60 I Clock: This PCI Bus clock provides timing for all bus phases. The rising edge defines the start of each phase. The clock frequency ranges from 0 to 33 MHz. DEVSELN 95 I/O Device Select: As a bus master, the DP83816 samples this signal to insure that the destination address for the data transfer is recognized by a PCI target. As a target, the DP83816 asserts this signal low when it recognizes its address after FRAMEN is asserted. FRAMEN 91 I/O Frame: As a bus master, this signal is asserted low to indicate the beginning and duration of a bus transaction. Data transfer takes place when this signal is asserted. It is de-asserted before the transaction is in its final phase. As a target, the device monitors this signal before decoding the address to check if the current transaction is addressed to it. GNTN 63 I Grant: This signal is asserted low to indicate to the DP83816 that it has been granted ownership of the bus by the central arbiter. This input is used when the DP83816 is acting as a bus master. IDSEL 76 I Initialization Device Select: This pin is sampled by the DP83816 to identify when configuration read and write accesses are intended for it. INTAN 61 O Interrupt A: This signal is asserted low when an interrupt condition occurs as defined in the Interrupt Status Register, Interrupt Mask, and Interrupt Enable registers. IRDYN 92 I/O Initiator Ready: As a bus master, this signal will be asserted low when the DP83816 is ready to complete the current data phase transaction. This signal is used in conjunction with the TRYDN signal. Data transaction takes place at the rising edge of PCICLK when both IRDYN and TRDYN are asserted low. As a target, this signal indicates that the master has put the data on the bus. PAR 99 I/O Parity: This signal indicates even parity across AD[31-0] and CBEN[3-0] including the PAR pin. As a master, PAR is asserted during address and write data phases. As a target, PAR is asserted during read data phases. PERRN 97 I/O Parity Error: The DP83816 as a master or target will assert this signal low to indicate a parity error on any incoming data (except for special cycles). As a bus master, it will monitor this signal on all write operations (except for special cycles). REQN 64 O Request: The DP83816 will assert this signal low to request ownership of the bus from the central arbiter. RSTN 62 I Reset: When this signal is asserted all PCI bus outputs of DP83816 will be in TRI- STATE® and the device will be put into a known state. |
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