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CHRONTEL
CH7013A
201-0000-041
Rev. 1.0,
6/14/2000
11
Digital Video Interface (continued)
Note: The AX[7:0] data is ignored.
When IDF = 9 (YCrCb 8-bit mode), H and V sync signals can be embedded into the data stream. In this mode, the
embedded sync will follow the CCIR656 convention, and the first byte of the “video timing reference code” will be
assumed to occur when a Cb sample would occur if the video stream was continuous. This is delineated in Table9
shown below.
Table 7. RGB 16-bit Muliplexed Mode
IDF#
Format
2
16-bit RGB (16-8)
Pixel#
P0a
P0b
P1a
P1b
Bus Data
D[15]
G0[7]
A0[7]
G1[7]
A1[7]
D[14]
G0[6]
A0[6]
G1[6]
A1[6]
D[13]
G0[5]
A0[5]
G1[5]
A1[5]
D[12]
G0[4]
A0[4]
G1[4]
A1[4]
D[11]
G0[3]
A0[3]
G1[3]
A1[3]
D[10]
G0[2]
A0[2]
G1[2]
A1[2]
D[9]
G0[1]
A0[1]
G1[1]
A1[1]
D[8]
G0[0]
A0[0]
G1[0]
A1[0]
D[7]
B0[7]
R0[7]
B1[7]
R1[7]
D[6]
B0[6]
R0[6]
B1[6]
R1[6]
D[5]
B0[5]
R0[5]
B1[5]
R1[5]
D[4]
B0[4]
R0[4]
B1[4]
R1[4]
D[3]
B0[3]
R0[3]
B1[3]
R1[3]
D[2]
B0[2]
R0[2]
B1[2]
R1[2]
D[1]
B0[1]
R0[1]
B0[1]
R1[1]
D[0]
B0[0]
R0[0]
B0[0]
R1[0]
Table 8. YCrCb Multiplexed Mode
IDF#
Format
9
YCrCb 8-bit
Pixel#
P0a
P0b
P1a
P1b
P2a
P2b
P3a
P3b
Bus Data
D[7]
Cb0[7]
Y0[7]
Cr0[7]
Y1[7]
Cb2[7]
Y2[7]
Cr2[7]
Y3[7]
D[6]
Cb0[6]
Y0[6]
Cr0[6]
Y1[6]
Cb2[6]
Y2[6]
Cr2[6]
Y3[6]
D[5]
Cb0[5]
Y0[5]
Cr0[5]
Y1[5]
Cb2[5]
Y2[5]
Cr2[5]
Y3[5]
D[4]
Cb0[4]
Y0[4]
Cr0[4]
Y1[4]
Cb2[4]
Y2[4]
Cr2[4]
Y3[4]
D[3]
Cb0[3]
Y0[3]
Cr0[3]
Y1[3]
Cb2[3]
Y2[3]
Cr2[3]
Y3[3]
D[2]
Cb0[2]
Y0[2]
Cr0[2]
Y1[2]
Cb2[2]
Y2[2]
Cr2[2]
Y3[2]
D[1]
Cb0[1]
Y0[1]
Cr0[1]
Y1[1]
Cb2[1]
Y2[1]
Cr2[1]
Y3[1]
D[0]
Cb0[0]
Y0[0]
Cr0[0]
Y1[0]
Cb2[0]
Y2[0]
Cr2[0]
Y3[0]
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