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MSM54V25632A Datasheet(PDF) 4 Page - OKI electronic componets

Part # MSM54V25632A
Description  131,072-Word x 32-Bit x 2-Bank Synchronous Graphics RAM
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Manufacturer  OKI [OKI electronic componets]
Direct Link  http://www.oki.com
Logo OKI - OKI electronic componets

MSM54V25632A Datasheet(HTML) 4 Page - OKI electronic componets

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¡ Semiconductor
MSM54V25632A
PIN DESCRIPTION
*Notes:
1. When CS is set "High" at a clock transition from "Low" to "High", all inputs except CLK, CKE, DQM0,
DQM1, DQM2, and DQM3 are invalid.
2. When issuing an active, read or write command, the bank is selected by A9.
3. The auto precharge function is enabled or disabled by the A8 input when the read or write command is
issued.
A9
0
1
Active, read or write
Bank A
Bank B
A8
0
Operation
After the end of burst, bank A holds the active status.
A9
0
0
0
After the end of burst, bank B holds the active status.
1
1
After the end of burst, bank A is precharged automatically.
After the end of burst, bank B is precharged automatically.
1
1
4. When issuing a precharge command, the bank to be precharged is selected by the A8 and A9 inputs.
A8
0
0
1
A9
0
1
X
Operation
Bank A is precharged.
Bank B is precharged.
Both banks A and B are precharged.
CLK
Fetches all inputs at the "H" edge.
CKE
Masks system clock to deactivate the subsequent CLK operation.
If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is
deactivated. CKE should be asserted at least one cycle prior to a new command.
Row & column multiplexed.
Row address: RA0 – RA8
Column address: CA0 – CA7
RAS
CAS
WE
Functionality depends on the combination. For details, see the function truth table.
DQM0 -
DQM3
Masks the read data of two clocks later when DQM0 - DQM3 are set "H" at the "H" edge of the clock signal.
Masks the write data of the same clock when DQM0 - DQM3 are set "H" at the "H" edge of the clock signal.
Address
DQi
Data inputs/outputs are multiplexed on the same pin.
CS
Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE,
DQM0, DQM1, DQM2 and DQM3.
Selects bank to be activated during row address latch time and selects bank for precharge and read/
write during column address latch time. A9 = "L" : Bank A, A9 = "H" : Bank B
BA (A9)
DSF
DSF is part of the inputs of graphics command of the MSM54V25632A.
If DSF is inactive (Low level), MSM54V25632A operates just like SDRAM.


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