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25AA256-ISNG Datasheet(PDF) 11 Page - Microchip Technology |
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25AA256-ISNG Datasheet(HTML) 11 Page - Microchip Technology |
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11 / 26 page  2003 Microchip Technology Inc. Preliminary DS21822C-page 11 25AA256/25LC256 2.6 Write Status Register Instruction (WRSR) The Write Status Register instruction (WRSR) allows the user to write to the nonvolatile bits in the Status register as shown in Table 2-2. The user is able to select one of four levels of protection for the array by writing to the appropriate bits in the Status register. The array is divided up into four segments. The user has the ability to write-protect none, one, two, or all four of the segments of the array. The partitioning is controlled as shown in Table 2-3. The Write-Protect Enable (WPEN) bit is a nonvolatile bit that is available as an enable bit for the WP pin. The Write-Protect (WP) pin and the Write-Protect Enable (WPEN) bit in the Status register control the programmable hardware write-protect feature. Hard- ware write protection is enabled when WP pin is low and the WPEN bit is high. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is low. When the chip is hardware write-protected, only writes to nonvolatile bits in the Status register are disabled. See Table 2-4 for a matrix of functionality on the WPEN bit. See Figure 2-7 for the WRSR timing sequence. TABLE 2-3: ARRAY PROTECTION FIGURE 2-7: WRITE STATUS REGISTER TIMING SEQUENCE (WRSR) BP1 BP0 Array Addresses Write-Protected 00 none 01 upper 1/4 (6000h - 7FFFh) 10 upper 1/2 (4000h - 7FFFh) 11 all (0000h - 7FFFh) SO SI CS 9 1011 12131415 01 0 0 0 0 00 76 5 4 21 0 instruction data to Status register high-impedance SCK 0 2 34 56 7 1 8 3 Note: An internal write cycle (TWC) is initiated on the rising edge of CS after a valid write Status Register sequence. |
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