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LTC3828EG Datasheet(PDF) 10 Page - Linear Technology |
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LTC3828EG Datasheet(HTML) 10 Page - Linear Technology |
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10 / 32 page  10 LTC3828 3828f (Refer to Functional Diagram) OPERATIO Main Control Loop The IC uses a constant frequency, current mode step- down architecture with the two controller channels oper- ating 180 degrees out of phase. During normal operation, each top MOSFET is turned on when the clock for that channel sets the RS latch, and turned off when the main current comparator, I1, resets the RS latch. The peak inductor current at which I1 resets the RS latch is con- trolled by the voltage on the ITH pin, which is the output of each error amplifier EA. The VOSENSE pin receives the voltage feedback signal, which is compared to the internal reference voltage by the EA. When the load current in- creases, it causes a slight decrease in VOSENSE relative to the 0.8V reference, which in turn causes the ITH voltage to increase until the average inductor current matches the new load current. After the top MOSFET has turned off, the bottom MOSFET is turned on until either the inductor current starts to reverse, as indicated by current compara- tor I2, or the beginning of the next cycle. The top MOSFET drivers are biased from floating boot- strap capacitor CB, which normally is recharged during each off cycle through an external diode when the top MOSFET turns off. As VIN decreases to a voltage close to VOUT, the loop may enter dropout and attempt to turn on the top MOSFET continuously. The dropout detector de- tects this and forces the top MOSFET off for about 400ns every tenth cycle to allow CB to recharge. The main control loop is shut down by pulling the RUN pin low. When the RUN pin reaches 1.5V, the main control loop is enabled. When RUN1 is low, all controller functions are shut down, including the 5V regulator. Low Current Operation The FCB/PLLIN pin is a multifunction pin providing two functions: 1) to accept external clock signal; and 2) to select among three modes of light load operations. When the FCB/PLLIN pin voltage is below 0.8V, the controller forces continuous PWM current mode operation. In this mode, the top and bottom MOSFETs are alternately turned on to maintain the output voltage independent of direction of inductor current. When the FCB/PLLIN pin is below VINTVCC – 2V but greater than 0.8V, the controller enters Burst Mode operation. Burst Mode operation sets a minimum output current level before inhibiting the top switch and turns off the synchronous MOSFET(s) when the inductor current goes negative. This combination of requirements will, at low currents, force the ITH pin below a voltage threshold that will temporarily inhibit turn-on of both output MOSFETs until the output voltage drops. There is 60mV of hysteresis in the burst comparator B tied to the ITH pin. This hysteresis produces output signals to the MOSFETs that turn them on for several cycles, followed by a variable “sleep” interval depending upon the load current. The resultant output voltage ripple is held to a very small value by having the hysteretic comparator after the error amplifier gain block. When the FCB/PLLIN pin voltage is above 4.8V, the controller operates in constant frequency mode and the synchro- nous MOSFET is turned off when inductor current nears zero in each cycle. In order to prevent erratic operation if no external connec- tions are made to the FCB/PLLIN pin, the FCB/PLLIN pin has a 0.18 µA internal current source pulling the pin high. The following table summarizes the possible states avail- able on the FCB/PLLIN pin: Table 1 FCB/PLLIN Pin Condition 0V to 0.75V Forced Continuous Both Controllers (Current Reversal Allowed— Burst Inhibited) 0.85V < VFCB/PLLIN < 4.3V Minimum Peak Current Induces Burst Mode Operation No Current Reversal Allowed >4.8V Burst Mode Operation Disabled Constant Frequency Mode Enabled No Current Reversal Allowed No Minimum Peak Current Besides providing a logic input to force continuous operation, the FCB/PLLIN pin acts as the input for exter- nal clock synchronization. Upon detecting the presence of an external clock signal, channel 1 will lock on to this external clock and this will be followed by channel 2 (see Frequency Synchronization section). The LTC3828 de- faults to forced continuous mode when sychronized to an external clock. |
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