CY7C1298F datasheet(11/15 Pages) CYPRESS

Part #	CY7C1298F

Description	1-Mbit (64K x 18) Pipelined DCD Sync SRAM

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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11 / 15 page

CY7C1298F

Document #: 38-05417 Rev. *A

Page 11 of 15

Write Timing[16,17]

Note:

17. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:B] LOW.

Switching Waveforms (continued)

tCYC

tCL

CLK

ADSP

tADH

tADS

ADDRESS

tCH

OE

ADSC

CE

tAH

tAS

A1

tCEH

tCES

BWE,

BW[A:B]

ADV

BURST READ

BURST WRITE

D(A2)

D(A2 + 1)

D(A3)

D(A3 + 1)

D(A3 + 2)

D(A2 + 3)

A2

A3

Extended BURST WRITE

D(A2 + 2)

Single WRITE

tADH

tADS

tADH

tADS

t

OEHZ

tADVH

tADVS

tWEH

tWES

t

DH

t

DS

GW

tWEH

tWES

Byte write signals are ignored for first cycle when

ADSP initiates burst

ADSC extends burst

ADV suspends burst

DON’T CARE

UNDEFINED

D(A1)

High-Z

Data in (D)

Data Out (Q)

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CY7C1298F Datasheet(PDF) 11 Page - Cypress Semiconductor

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