SST™ SONET/SDH Serial Transceiver
CY7B952
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-02018 Rev. *B
Revised April 27, 2004
Features
• OC-3 Compliant with Bellcore and CCITT (ITU) specifi-
cations on:
—Jitter Generation (<0.01 UI)
— Jitter Transfer (<130 kHz)
— Jitter Tolerance
• SONET/SDH and ATM Compliant
• Compatible with IGT WAC013, IGT WAC413, and
PMC-Sierra PM5343
• Clock and data recovery from 51.84- or 155.52-MHz
datastream
• 155.52-MHz clock multiplication from 19.44-MHz source
• 51.84-MHz clock multiplication from 6.48-MHz source
•
±1% frequency agility
• Line Receiver Inputs: No external buffering required
• Differential output buffering
• 100K ECL compatible I/O
• No output clock “drift” without data transitions
• Link Status Indication
• Loop-back testing
• Single +5V supply
•24-pin SOIC
• Compatible with fiber-optic modules, coaxial cable, and
twisted pair media
• Power-down options to minimize power or crosstalk
• Low operating current: <70 mA
• 0.8
µ BiCMOS
Functional Description
The SONET/SDH Serial Transceiver (SST) is used in
SONET/SDH and ATM applications to recover clock and data
information from a 155.52-MHz or 51.84-MHz NRZ or NRZI
serial data stream and to provide differential data buffering for
the Transmit side of the system.
Figure 1. SONET/SDH Overhead Processing Application
PLL
TCLK–
TCLK+
REFCLK+
TRANSMIT
MODE
LFI(t)
FC–
FC+
TSER–
TSER+
RSER–
RSER+
RCLK–
RCLK+
LOOP(t)
TOUT–
TOUT+
x8
RECEIVE
RIN–
RIN+
REFCLK–
PLL
CD
TCLK+
REFCLK+
FC+
FC–
RIN+
RIN–
MODE
VCC
CD
LOOP
REFCLK–
TOUT–
TOUT+
RCLK–
RCLK+
RSER–
RSER+
LFI
VCC
VSS
VCC
TCLK–
TSER+
TSER–
SOIC
Top View
1
2
3
4
5
6
7
8
9
10
11
12
15
16
17
18
19
20
24
23
22
21
13
14
CY7B952
Logic Block Diagram
Pin Configuration
SST
Path
CY7B952
Cypress
Recovery
Clock/Data
Driver
Line
Transport
Overhead
Transceiver
Transceiver
Overhead
SONET/SDH
PMC-Sierra
PM5343STXC
PMC-Sierra
PM5344SPTX
SONET/SDH
S->P
P->S
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