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ASM1232LPSN Datasheet(PDF) 6 Page - Alliance Semiconductor Corporation |
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ASM1232LPSN Datasheet(HTML) 6 Page - Alliance Semiconductor Corporation |
6 / 10 page ASM1232LP/LPS 6 of 10 Notice: The information in this document is subject to change without notice 5V µP Power Supply Monitor and Reset Circuit January 2005 rev 1.5 Notes 1. PBRST is internally pulled HIGH to VCC through a nominal 40kΩ resistor. 2. RESET is an open drain output. 3. RESET remains within 0.5V of VCC on power-down until VCC falls below 2V. RESET remains within 0.5V of ground on power-down until VCC falls below 2.0V. 4. Must not exceed the minimum watchdog time-out period (tTD). The watchdogcircuit cannot be disabled. To avoid a reset, ST must be strobed. Input Leakage IIL Note 1 -1.0 1.0 µA RESET Low Level VOL Note 3 0.4 V Internal Pull-up Resistor Note 1 40 k Ω Operating Current (CMOS) ICC1 30 µA Input Capacitance CIN 5pF Output Capacitance COUT 10 pF PBRST Manual Reset Minimum Low Time tPB PBRST = VIL 20 ms Reset Active Time tRST 250 610 1000 ms ST Pulse Width tST Note 4 20 ns VCC Fail Detect to RESET or RESET tRPD 58 µs VCC Slew Rate tF 4.75V to 4.25V 300 µs PBRST Stable LOW to RESET and RESET Active tPDLY 20 ms VCC Detect to RESET or RESET inactive tRPU tRISE = 5µs 250 610 1000 ms VCC Slew Rate tR 4.25V to 4.75V 0 ns Parameter Symbol Conditions Min Typ Max Unit |
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