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GC4016-PB Datasheet(PDF) 10 Page - Texas Instruments

Part # GC4016-PB
Description  MULTI-STANDARD QUAD DDC CHIP
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

GC4016-PB Datasheet(HTML) 10 Page - Texas Instruments

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© GRAYCHIP,INC.
- 5 -
August 27, 2001
GC4016 MULTI-STANDARD QUAD DDC CHIP
DATA SHEET REV 1.0
This document contains information which may be changed at any time without notice
compensating for the droop in the CIC filter’s passband. The
second stage is a 63 tap decimate by 2 filter (PFIR) with user
programmable tap weights. The user can customize the
channel’s spectral response using the PFIR filter. A typical
use of the PFIR is to perform matched (root-raised cosine)
filtering. The 63 tap symmetrical filter is downloaded into the
chip as 32 words, 16 bits each. Both filters must be
programmed as there are no default filter coefficient sets.
The CIC, CFIR, and PFIR filters can all be configured in
a SPLITIQ mode where the channel only processes the real
portion of the mixer output. In this case the minimum CIC
decimation is 4. By using two channels in parallel one can
process twice the output bandwidth by processing the real
portion of the mixer output in one channel and the imaginary
portion in a second channel (hence the name “split I/Q”). One
can also offset the decimation timing between channels so
that two or even four channels can be used to generate
oversampled data. Using this capability each GC4016 chip
can downconvert wideband signals such as 4X oversampled
5.12 Msymbol/sec MCNS data, or 4X oversampled 5 MHz
WB-CDMA (UMTS) data, or two 8X oversampled NB-CDMA
IS95 signals.
The PFIR will also, if desired, convert the complex
output data to real. The complex to real conversion also
doubles the output sample rate so that the PFIR does not
decimate in this mode. This mode is useful when one wants
to output real data.
The PFIR filter is followed by a resampler. The
resampler filters the PFIR output to generate new sample
points in between the PFIR output samples. The resampler
is programmed to generate new output samples spaced in
time by “R” times the PFIR output’s sample period. The value
R is called the resampling ratio. If R is less than one, the
resampler will interpolate. If R is greater than one, the
resampler will decimate. The value of R is specified as a 32
bit word (6 integer bits and 26 fractional bits). The time
resolution of the new sampling points is user programmable
down to 1/64th of the PFIR output’s sample period. If R is a
multiple of the selected time resolution, then the resampling
process will have no resampling time jitter. If R is not a
multiple of the time resolution, then the output will be
generated at the time instant closest to the desired output
time.
The resampler is typically used to either generate
oversampled output data (for instance 4x oversampled
QPSK or GMSK data), or to alter the sampler rate to match
a multiple of the baud rate of a QPSK or GMSK signal. The
resampling operation allows the user to design a system
where the ADC sample rate does not need to be equal to an
integer multiple of the baud rate of the desired output signal.
The resampler can also be used as a final filtering stage.
A final shift circuit allows the user to shift the data by up
to 15 bits to properly place it in the output word. The output
word may be rounded to 12,16, 20, or 24 bits.
The data may be output from the chip via a
microprocessor interface, serial pins, or using a parallel port.
The parallel port is particularly valuable for wideband output
data.
3.3.1 Zero Padding
The input samples are normally clocked into the chip at
the clock rate, i.e., the input sample rate is equal to the clock
rate. Input rates lower than the clock rate can be accepted by
using the zero pad mode. When enabled by setting the
ZPAD_EN bit in address 19 of the channel control pages, the
zero pad mode will insert “NZERO” zeroes between each
input sample, where NZERO ranges from 0 to 15, allowing
input data rates down to 1/16th the clock rate. NZERO is set
in address 19
NCO
TUNING
FREQUENCY
PHASE
OFFSET
IN
TO
OUTPUT
CIRCUIT
Q
I
20
24
20
20
24
12,16, 20 or 24 bits
20
Figure 4. The Down Converter Channel


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