For SFP/SFF, FDDI, 155Mbps ATM LAN, Fast Ethernet,

0.01µF. This capacitor value ensures chatter-free

LOS/SD and provides a typical assert/deassert time of

be calculated using the following equation:

τ / 825Ω

where

τ is the desired time constant of the power detector.

data inputs for the offset correction loop to function

properly. The offset correction loop bandwidth is deter-

at the lower -3dB corner frequency. For SFP/SFF, FDDI,

155Mbps ATM LAN, Fast Ethernet, and ESCON

receivers, Maxim recommends the following:

200Mbps SFP Limiting Amplifier

_______________________________________________________________________________________

7

OUT-

OUT+

ESD

STRUCTURES

Figure 2. Equivalent PECL Output Circuit

LOS/LOS

ESD

STRUCTURES

Figure 3. Equivalent TTL Output Circuit

PIN-TIA RESPONSIVITY = G

1.8dB

2.5dB

10 log(OPTICAL POWER)

RX_MAX (SENSITIVITY)

SD HIGH / LOS LOW

SD LOW / LOS HIGH

5dB

3.6dB

Figure 4. Signal Levels for Power-Detect Threshold