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IDT71V547S80PFI Datasheet(PDF) 6 Page - Integrated Device Technology |
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IDT71V547S80PFI Datasheet(HTML) 6 Page - Integrated Device Technology |
6 / 19 page 6 IDT71V547, 128K x 36, 3.3V Synchronous SRAM with ZBT ™ ™ ™ ™ ™ Feature, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges Functional Timing Diagram(1) NOTE: 1. This assumes CEN, CE1, CE2 and CE2 are all true. 2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data delay from the rising edge of clock. n+29 A29 C29 D/Q28 ADDRESS (A0 - A16) CONTROL (R/W ,ADV/LD , BW x) DATA I/O [0:31], I/O P[1:4] CYCLE CLOCK n+30 A30 C30 D/Q29 n+31 A31 C31 D/Q30 n+32 A32 C32 D/Q31 n+33 A33 C33 D/Q32 n+34 A34 C34 D/Q33 n+35 A35 C35 D/Q34 n+36 A36 C36 D/Q35 (2) (2) (2) 3822 drw 03 A37 C37 D/Q36 n+37 ., Linear Burst Sequence Table (LBO=VSS) Interleaved Burst Sequence Table (LBO=VDD) NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting. Sequence 1 Sequence 2 Sequence 3 Sequence 4 A1 A0 A1 A0 A1 A0 A1 A0 First Address 0 00 11 0 1 1 Second Address 0 1 0 0 1 1 1 0 Third Address 1 0 1 1 0 0 0 1 Fourth Address(1) 11 1 0 0 1 00 3822 tbl 09 NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting. Sequence 1 Sequence 2 Sequence 3 Sequence 4 A1 A0 A1 A0 A1 A0 A1 A0 First Address 0 0 0 1 1 0 1 1 Second Address 0 1 1 0 1 1 0 0 Third Address 1 0 1 1 0 0 0 1 Fourth Address(1) 11 00 0 1 1 0 3822 tbl 10 |
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