HY62UF08401C Series

Rev.02 / Jun.01

5

TIMING DIAGRAM

READ CYCLE 1 (Note 1,4)

READ CYCLE 2 (Note 1,2,4)

tRC

tAA

Data Valid

Previous Data

tOH

tOH

ADDR

Data

Out

READ CYCLE 3(Note 1,2,4)

/CS

tACS

Data Valid

tCLZ(3)

tCHZ(3)

Data

Out

Notes:

1. A read occurs during the overlap of a low /OE, a high /WE and a low /CS.

3. Transition is measured + 200mV from steady state voltage.

This parameter is sampled and not 100% tested.

4. /CS in high for the standby, low for active

ADDR

tRC

/CS

tAA

tACS

tOH

Data Valid

High-Z

Data

Out

/OE

tOE