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ISPPAC20-01JI Datasheet(PDF) 7 Page - Lattice Semiconductor

Part # ISPPAC20-01JI
Description  In-System Programmable Analog Circuit
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Manufacturer  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

ISPPAC20-01JI Datasheet(HTML) 7 Page - Lattice Semiconductor

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Specifications ispPAC20
7
valid data
tcsw
tdacs
tdach
CS
DAC
D0-D7
Timing Specifications (SPI/Parallel Interface Modes), Continued
CS
TCK
TDI
TDO
LSB
MSB
don’t
care
don’t
care
DI0
Represents previous data in shift register
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DO0
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
SS
MISO
MOSI
SCK
TCK
TDI
TDO
CS
+5V
ENSPI
ispPAC20
SPI
MASTER
DAC Parallel Input Timing Specifications
SPI Connection Diagram
SPI Data Transfer
Notes
1.
SPI data is loaded in TDI, LSB first. If TCK continues to clock after
CS goes high, data will continue to be shifted through the shift register,
even though the TDO pin is tristated after
CS goes high.
2.
DO0 –> DO7 represents “data out” from the SPI microprocessor or other digital source to the TDI input of the ispPAC20.
3.
DI0 –> DI7 represents “data in” from the ispPAC20 TDO pin to the SPI microprocessor input or other digital source.
4.
After the eighth clock, the LSB (DO0) is valid on TDO as long as CS is low.


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