Preliminary W27L520

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FUNCTIONAL DESCRIPTION

Read Mode

Unlike conventional UVEPROMs, which has CE and OE two control functions, the W27L520 has one

to be latched in the chip when it goes from high to low, so that the same bus can be used to output

controls the output buffer to gate data to the output pins. When addresses are stable, the address

Erase Mode

The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs,

which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half

an hour), the W27L520 uses electrical erasure. Generally, the chip can be erased within 100 mS by

using an EPROM writer with a special erase algorithm.

or high. Pulsing ALE high starts the erase operation. The other way is somewhat like flash, by

programming two consecutive commands into the device and then enter Erase mode. The two

commands are loading Data = AA(hex) to Addr. = 5555(hex) and Data = 10(hex) to Addr. =

2AAA(hex). Be careful to note that the ALE pulse widths of these two commands are different: One is

50uS, while the other is 100mS. Please refer to the Smart Erase Algorithm 1 & 2.

Erase Verify Mode

The device will enter the Erase Verify Mode automatically after Erase Mode. Only power down the

device can force the device enter Normal Read Mode again.

Program Mode

Programming is the only way to change cell data from "1" to "0." The program mode is entered when

the input pins equal the desired inputs. Pulsing ALE high starts the programming operation.

Program Verify Mode

The device will enter the Program Verify Mode automatically after Program Mode. Only power down

the device can force the device enter Normal Read Mode again.

Erase/Program Inhibit

Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different

data. When ALE low, erasing or programming of non-target chips is inhibited, so that except for the

Standby Mode

keep high. In standby mode, all outputs are in a high impedance state.

System Considerations