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June 24, 2002
IDT77010
Input Control Cell Formatting
Input Control Cell Formatting
Input Control Cell Formatting
Input Control Cell Formatting
Control cells are generated by a remote computer and are used to
configure and monitor the PHY registers. All cells having the header VPI
= 0x00 hex and VCI = 0x1F hex (VCI bits 11-4) are decoded and
executed as control cells by the 77010.
Control Cell Filter Operation
Control Cell Filter Operation
Control Cell Filter Operation
Control Cell Filter Operation
All cells transferred over the DTxDATA[3:0] bus are tested to see if
they are control cells.Cells containing the header VPI = 00 Hex and VCI
= 1F Hex (VCI bits 11-4) are filtered as control cells and not forwarded to
the TxDATA[7:0] bus. The filter ignores the GFC, PTI and CLP bits. The
default control cell identifier value is 00x1F. It can be programmed to a
user defined value via the Change Control Cell Address Command (see
page 16).
Control Cell Frequency
Control Cell Frequency
Control Cell Frequency
Control Cell Frequency
The control cells arrive multiplexed with data cells in random combi-
nations, and are terminated (filtered) by the 77010.
The RxDATA[3:0] bus multiplexes the receive UTOPIA cells and any
internally generated control cells. The control cell is ignored if a previous
control cell is being executed at that time. A gap in the UTOPIA cell
stream must occur before the new control cell is processed, because the
UTOPIA receive cells have higher priority.
Control cells may be input back-to-back. However, the second
control cell will not be processed and could be dropped, even though the
77010 can filter both of them. Worst case condition is when the receive
UTOPIA bus is at full rate. In this case it is recommended that the
control cells be at least 50 cells apart.
DPI Interface Operation
DPI Interface Operation
DPI Interface Operation
DPI Interface Operation
Data Path Interface (DPI) is a synchronous bus interface designed to
transfer ATM cells between two devices. The 77010 contains a DPI-4
bus interface, which contains a four bit wide data bus. Therefore, 107
clock cycles are required to transfer a 53 byte ATM cell.
The 77010 has separate DPI-4 transmit and receive interfaces, with
each requiring six signals. The signals are a clock, a start of cell marker
and a four bit data bus. All signals are sampled on the rising edge of
their respective clock.
Transmit DPI Bus Interface
Transmit DPI Bus Interface
Transmit DPI Bus Interface
Transmit DPI Bus Interface
The Transmit DPI Clock (DTxCLK) is generated from SYSCLK and is
twice the frequency of TCLK. This clock is not continuous and is used to
control data flow to the PHY device. DTxCLK is initially low and not
driven until the 77010 detects a high TCLAV from the PHY device. On
the rising edge of DTxCLK the 77010 samples Transmit Start of Cell
(DTxFRM), which is generated by the transmitting device for one
DTxCLK cycle. When DTxFRM is asserted high the 77010 will sample
valid data (DTxDATA[3:0]) on the next rising edge of DTxCLK. Cell
transfer will continue without interruption once it has started.
When TCLAV is de-asserted low the current cell is transferred and
DTxCLK goes low until another high TCLAV is detected.
DTxFRM and DTxDATA[3:0] are sampled on the rising edge of
DTxCLK.
Control ATM Cell Format
Control ATM Cell Format
Control ATM Cell Format
Control ATM Cell Format
Cell Byte
Number
Bit
Number
Function
Name
Bit
Contents
Description
0
7-4
GFC
0xX
Don't care.
0
3-0
VPI 7-4
0x0
Must be set to 0x0.
1
7-4
VPI 3-0
0x0
Must be set to 0x0.
1
3-0
VCI 15-12
0x0
Must be set to 0x0.
2
7-0
VCI 11-4
0xYY
Special VCI value for control and status cells. Default is 0x1F.1
3
7-4
VCI 3-0
0x0
Don't care.
3
3-1
PTI
000'b
Don't care.
3
0
CLP
0'b
Don't care.
4
7-0
HEC
0x00
Don't care.
5
7-0
Command
00-FF Hex
Command cell byte.
6
7-0
Data A
0x0 - 0xFF
Parameter for control cell.
7
7-0
Data B
0x0 - 0xFF
Parameter for control cell.
8
7-0
reserved
0x00
Always set to 0x00.