3 of 21
June 24, 2002
IDT77010
Pin Definitions
Pin Definitions
Pin Definitions
Pin Definitions
Signal Name
Pin
Number
Input/
Output
Description
SysClk
29
I
System Clock. All the device circuits are synchronized to this clock.
RST
23
I
System Reset. When low the 77010 and the PHY are reset. This is used as a global line card reset where all
the RST signals from all line cards are connected together.
LCRST
24
I
Line Card reset. When low the 77010 and the PHY are reset. This is a local line card reset used to reset a
specific 77010 and PHY on a specific line card.
CONT_A
19
O
Output Control Pin A. This pin is controlled by a receive control cell. Default output = low.
CONT_B
22
O
Output Control Pin B. This pin is controlled by a receive control cell. Default output = low.
RxLED
42
O
Active low. When low a receive cell is being transferred.
This pin may be used for receive activity LED.
TxLED
79
O
Active low. When low a transmit cell is being transferred.
This pin may be used for transmit activity LED.
READ
73
O
Utility bus read signal.
WRITE
74
O
Utility bus write signal.
ALE
59
O
Utility bus address latch enable. Used for latching the address on the address phase of the Add/Data bus.
Add/Data0
71
I/O
Utility bus multiplexed address and data bus.
Add/Data1
70
I/O
Utility bus multiplexed address and data bus.
Add/Data2
69
I/O
Utility bus multiplexed address and data bus.
Add/Data3
68
I/O
Utility bus multiplexed address and data bus.
Add/Data4
65
I/O
Utility bus multiplexed address and data bus.
Add/Data5
64
I/O
Utility bus multiplexed address and data bus.
Add/Data6
63
I/O
Utility bus multiplexed address and data bus.
Add/Data7
62
I/O
Utility bus multiplexed address and data bus.
PHYCS
78
O
Utility bus PHY chip select.
PHYINT
72
I
Utility bus PHY interrupt signal
PHYRST
77
O
Utility bus PHY reset.
RCLK
45
O
UTOPIA bus receive clock.
RSOC
58
I
UTOPIA bus receive start of cell.
RENB
43
O
UTOPIA bus receive enable.
RCLAV
44
I
UTOPIA bus receive cell available.
RxData0
46
I
UTOPIA bus receive data bit.
RxData1
49
I
UTOPIA bus receive data bit.
RxData2
50
I
UTOPIA bus receive data bit.
RxData3
51
I
UTOPIA bus receive data bit.
RxData4
52
I
UTOPIA bus receive data bit.
RxData5
53
I
UTOPIA bus receive data bit.
RxData6
54
I
UTOPIA bus receive data bit.
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