8-Bit Programmable Filters
818 Series
Digital Tuning &
Control Characteristics
25 Locust St, Haverhill, Massachusetts 01830 • Tel: 800/252-7074, 978/374-0761 • FAX: 978/521-1839
e-mail: sales@freqdev.com • Web Address: http://www.freqdev.com
2
MSB
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LSB
27
26
25
24
23
22
21
20
D7
D6
D5
D4
D3
D2
D1
D0
00000000
fmax/256
00000001
fmax/128
00000011
fmax/64
00000111
fmax/32
00001111
fmax/16
00011111
fmax/8
00111111
fmax/4
01111111
fmax/2
11111111
fmax
Bit
Weight
fc
Corner
Frequency
+Vs
OUT
-Vs
D
D
D
D
GND
D
D
D
D
C
P
IN
Bottom View
Os/NC
4
5
3
2
1
0
6
7
Pin-Out Key
IN
Analog Input Signal
D7 Tuning Bit 7 (MSB)
OUT Analog Output Signal
D6 Tuning Bit 6
GND Power and Signal Return
D5 Tuning Bit 5
"P"
Transition Polarity Bit
D4 Tuning Bit 4
"C"
Tuning Strobe Bit
D3 Tuning Bit 3
+Vs
Supply Voltage, Positive
D2 Tuning Bit 2
-Vs
Supply Voltage, Negative
D1 Tuning Bit 1
Os
Optional Offset Adjustment
D0 Tuning Bit 0 (LSB)
NC
No Connect (Highpass Models)
Digital Tuning Characteristics
The digital tuning interface circuits are two 4042 quad CMOS
latches which accept the following CMOS-compatible inputs:
eight tuning bits (D
0 - D7), a latch strobe bit (C), and a transition
polarity bit (P).
Filter tuning follows the tuning equation given below:
fc = ( fmax/256 ) [ 1 + D
7 x 2
7
+ D
6 x 2
6
+ D
5 x 2
5
+ D
4 x 2
4
+ D
3 x
2
3
+ D
2 x 2
2
+ D
1 x 2
1
+ D
0 x 2
0
]
where D
1 - D7 = "0" or "1", and
fmax = Maximum tuning frequency;
fc = corner frequency;
Minimum tunable frequency = fmax/256 (D
0 thru D7 = 0);
Minimum frequency step (Resolution) = fmax/256
Data Control Specifications
Data Control Lines
Functions
Latch Strobe (C)
Transition Polarity (P)
Data Control Modes
Mode 1
P = 0; C = 0 frequency follows input codes
P = 0; C = 0
⇑ frequency latched on rising edge
Mode 2
P = 1; C = 1 frequency follows input codes
P = 1; C = 1
⇓ frequency latched on falling edge
Input Data Levels
(CMOS Logic)
Input Voltage (Vs = 15 Vdc)
Low Level In
0 Vdc min.
4 Vdc max.
High Level In
11 Vdc min.
15 Vdc max.
Input Current
High Level In
- 10
-5 µA typ. -1 mA max.
Low Level In
+10
-5 µA typ.
+1
µA max.
Input Capacitance
5 pF typ
7.5 pF max.
Latch Response
Data Set Up Time
1
25 nS
Data Hold Time
2
50 nS
Strobe Pulse Width
80 nS min.
Input Data Format
Frequency Select Bits
Positive Logic
Logic "1" = +Vs
Logic "0" = Gnd
Bit Weighting
(Binary-Coded)
D
0
LSB (least significant bit)
D
7
MSB (most significant bit)
Frequency Range
256 : 1, Binary Weighted
Notes:
1.Frequency data must be present before occurrence of strobe edge.
2.Frequency data must be present after occurrence of strobe edge.