SCD1283 datasheet(6/94 Pages) INTEL

Part #	SCD1283

Description	IEEE 1284-Compatible Parallel Interface

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Manufacturer	INTEL [Intel Corporation]

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CD1283 — IEEE 1284-Compatible Parallel Interface

6

Datasheet

Figures

1

Functional Block Diagram ................................................................................... 10

2

Functional Block Diagram ................................................................................... 23

3

Internal Address Generation ............................................................................... 23

4

CD1283 Daisy-Chain Configuration .................................................................... 26

5

Interrupt Generation Logic .................................................................................. 28

6

Control Signal Generation ................................................................................... 31

7

FIFO Data Path Functional Diagram – Receive .................................................. 37

8

FIFO Data Path Functional Diagram: Transmit ................................................... 38

9

Supported Compatibility Mode Timing ................................................................ 40

10

Cable Connection................................................................................................ 43

11

External Buffer Control........................................................................................ 44

12

Sample System Block Diagram........................................................................... 44

13

Intel‚ 80x86 Family Interface ............................................................................... 45

14

Motorola‚ 68020 Interface ................................................................................... 46

15

Flow Diagram of the CD1283 Master Initialization Sequence ............................. 48

16

Polling Flow Chart ............................................................................................... 51

17

Reset Timing ....................................................................................................... 79

18

Clock Timing ....................................................................................................... 80

19

Asynchronous Read Cycle Timing ...................................................................... 80

20

Asynchronous Write Cycle Timing ...................................................................... 81

21

Asynchronous Service Acknowledge Cycle Timing ............................................ 82

22

Asynchronous DMA Read Cycle Timing ............................................................. 83

23

Asynchronous DMA Read Cycle Timing (Two Back-to-Back DMA Reads) ........ 83

24

Asynchronous DMA Write Cycle Timing ............................................................. 84

25

Asynchronous DMA Write Cycle Timing ............................................................. 84

26

Synchronous Read Cycle Timing ........................................................................ 86

27

Synchronous Write Cycle Timing ........................................................................ 87

28

Synchronous Service Acknowledge Cycle Timing .............................................. 88

29

Synchronous DMA Write Cycle Timing

(Two Back-to-Back 3-Cycle DMA Writes) ........................................................... 89

30

Synchronous DMA Read Cycle Timing

(Two Back-to-Back 3-Cycle DMA Reads) ........................................................... 89

Tables

1

Global Registers.................................................................................................. 19

2

Virtual Registers.................................................................................................. 20

3

Parallel Pipeline Registers .................................................................................. 20

4

Parallel Port Registers ........................................................................................ 20

5

Special Register .................................................................................................. 21

6

LIVR[2:0] Encoding ............................................................................................. 31

7

System Clock Setup ............................................................................................ 42

8

Hexadecimal — Character .................................................................................. 51

9Decimal — Character.......................................................................................... 52

10

PIVR[2:0] Encoding............................................................................................. 56

11

SPR Binary Values to Set 500-ns Pulse Widths ................................................. 74

12

Asynchronous Timing Reference Parameters .................................................... 78

13

Synchronous Timing Reference Parameters ...................................................... 85

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