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IDT72V7280L15 Datasheet(PDF) 2 Page - Integrated Device Technology |
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IDT72V7280L15 Datasheet(HTML) 2 Page - Integrated Device Technology |
2 / 42 page 2 COMMERCIALTEMPERATURERANGE IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO 512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72 PIN CONFIGURATION PBGA (BB256-1, order code: BB) TOP VIEW DESCRIPTION: The IDT72V7230/72V7240/72V7250/72V7260/72V7270/72V7280/ 72V7290/72V72100areexceptionallydeep,highspeed,CMOSFirst-In-First- Out (FIFO) memories with clocked read and write controls and a flexible Bus- Matching x72/x36/x18 data flow. These FIFOs offer several key user benefits: • Flexible x72/x36/x18 Bus-Matching on both read and write ports • The period required by the retransmit operation is fixed and short. • The first word data latency period, from the time the first word is written to an empty FIFO to the time it can be read, is fixed and short. • High density offerings up to 4 Mbit Bus-Matching Sync FIFOs are particularly appropriate for network, video, telecommunications,datacommunicationsandotherapplicationsthatneedto buffer large amounts of data and match busses of unequal sizes. Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume either a 72-bit, 36-bit or a 18-bit width as determined by the state of external control pins Input Width (IW), Output Width (OW), and Bus- Matching (BM) pin during the Master Reset cycle. TheinputportiscontrolledbyaWriteClock(WCLK)inputandaWriteEnable ( WEN)input. DataiswrittenintotheFIFOoneveryrisingedgeofWCLKwhen WEN isasserted. TheoutputportiscontrolledbyaReadClock(RCLK)input A B C D E F G H J K L M N P R T Q33 Q32 Q31 Q29 Q17 Q14 Q11 Q62 Q59 Q56 Q44 Q41 Q38 Q26 Q24 Q23 Q35 Q34 Q30 Q28 Q16 Q13 Q10 Q61 Q58 Q55 Q43 Q40 Q37 Q25 Q21 Q22 Q47 Q46 Q45 Q27 Q15 Q12 Q9 Q60 Q57 Q54 Q42 Q39 Q36 Q18 Q19 Q20 Q50 Q49 Q48 SEN D51 D52 D53 GND LD D3 D4 D5 D63 D64 D65 D0 D1 D2 D66 D67 D68 GND PRS WEN REN D69 D70 D71 TDI IP RCS EF FF Q69 Q70 Q71 TCK BE Q0 PAE RCLK Q66 Q67 Q68 GND VCC Q2 WCLK PAF D47 D46 D45 VCC HF Q1 OE MRS D6 D7 D8 GND VCC Q3 Q4 Q5 D50 D49 D48 VCC Q6 Q7 Q8 Q63 Q64 Q65 D27 D15 D12 D9 D60 D57 D54 D42 D39 D36 D18 D19 D20 Q51 Q52 Q53 D28 D16 D13 D10 D61 D58 D55 D43 D40 D37 D25 D21 D22 D33 D32 D31 D29 D17 D14 D11 D62 D59 D56 D44 D41 D38 D26 D24 D23 12 3456 7 8 9 10 11 12 13 14 15 16 A1 BALL PAD CORNER GND GND GND GND GND GND VCC TRST VCC VCC VCC VCC VCC VCC VCC FS0 TDO GND GND GND GND GND GND GND OW TMS VCC VCC VCC VCC VCC VCC GND VCC GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC GND GND GND GND GND GND GND FS1 GND GND VCC VCC VCC VCC VCC BM GND GND GND GND GND GND PFM RT VCC VCC VCC VCC VCC VCC FWFT/ SI RM GND 4680 drw02 GND SCLK D35 D34 D30 IW |
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