VCXO-Based Clock Translator with High Multiplication

MDS 2069-03 I

8

Revision 050203

www.icst.com

MK2069-03

Example Loop Filter Component Value

Notes:

1) This filter configuration assures a passband ripple compliant with Bellcore GR-1244-CORE to satisfy

wander transfer requirements (<0.2 dB ripple is required) of a network node. It can be used following a

system synchronizer such as the MT9045 to provide clock jitter attenuation while maintaining Stratum 3

compliance. A 155.52 MHz TCLK output generated with the VCXO PLL configuration will be OC-3 and OC-12

timing jitter compliant.

GR-1244-CORE compliance is not needed.

3) This configuration is used to generate a DS3 clock of 44.736 MHz at the TCLK output. This configuration

is GR-1244-CORE compliant when used following a system synchronizer.

Loop Filter Capacitor Type

Loop filters must use specific types of capacitors.

Recommendations for these capacitors can be found at

www.icst.com.

10

20

1 5

25

30

2000

3000

4000

5000

6000

1000

C rystal F requ e ncy, M H z

Phase

Detector

Frequency

Xtal

Freq

(MHz)

SV

Div

VCLK

(MHz)

FV Div x

FPV Div

Loop

BW

(-3dB)

Loop

Damp.

Passband

Peaking

Note

8 kHz

19.44

1

19.44

2430

1 M

Ω 560 kΩ 1 µF

4.7 nF

22 Hz

4.0

0.15dB at 1Hz

1

8 kHz

19.44

1

19.44

2430

1 M

Ω 560 kΩ 0.1 µF 4.7 nF 27 Hz

1.4

1.2dB at 6Hz

2

8 kHz

22.368

1

22.368

2796

1 M

Ω 680 kΩ 1 µF

4.7 nF

20 Hz

4.5

0.12dB at 1Hz

3