MK2069-03 datasheet(2/19 Pages) ICST

Part #	MK2069-03

Description	VCXO-Based Clock Translator with High Multiplication

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Manufacturer	ICST [Integrated Circuit Systems]

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VCXO-Based Clock Translator with High Multiplication

MDS 2069-03 I

2

Revision 050203

Integrated Circuit Systems, Inc. l 525 Race Street, San Jose, CA 95126 l tel (408) 295-9800 l

www.icst.com

MK2069-03

Pin Assignment

VCXO PLL Feedback Pre-Divider Selection

VCXO PLL Feedback Divider Selection

VCXO PLL Scaling Divider Selection Table

Translator PLL Reference Divider Selection

Table

Translator PLL Feedback Divider Selection

Translator PLL Scaling Divider Selection Table

FPV5:0 FPV Divider Ratio

Notes

000000

2

FPV Divide = Address + 2

000001

3

::

111111

65

21

FV0

22

FV1

23

FV2

24

FV3

1

ST 0

2

ST 1

3

RT 0

4

RT 1

5

FT 0

6

FT 1

7

FT 2

8

FT 3

9

FT 4

10

FT 5

11

FPV0

12

VD D T

13

GN D T

14

X1

15

V DDV

16

X2

17

GN D V

18

LF R

19

LF

20

ISET

25

FV4

26

FV5

27

FV6

28

FV7

36

35

34

33

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

32

31

30

29

CL R

IC L K

FPV2

FPV1

SV 2

SV 1

SV 0

FPV5

FPV4

FPV3

OE L

OE T

OE V

OE R

VD D

LD

TC LK

VD D P

VC LK

GN D P

RC L K

LD R

GN D

LD C

FV1 1

FV1 0

FV9

FV8

FV11:0 FV Divider Ratio

Notes

0...00

2

For FV addresses 0 to 4094,

FV Divide = Address + 2

0...01

3

::

1...10

4096

1...11

1

SV2

SV1

SV0

SV Divider Ratio

00

0

4

00

1

6

01

0

8

01

1

10

0

12

10

1

2

11

0

16

11

1

RT1

RT0

RT Divider Ratio

00

2

01

3

10

4

11

1

FT5:0

FT Divider Ratio

Notes

000000

2

For FT addresses 0 to 62,

FT Divide = Address + 2

000001

3

::

111110

64

111111

1

ST1

ST0

ST Divider Ratio

00

2

01

4

10

8

11

16

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