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ICS950508YFLF-T Datasheet(PDF) 1 Page - Integrated Circuit Systems |
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ICS950508YFLF-T Datasheet(HTML) 1 Page - Integrated Circuit Systems |
1 / 19 page Integrated Circuit Systems, Inc. ICS950508 0470E—04/06/05 Block Diagram Pin Configuration Recommended Application: 810/810E/815 and 815 B-Step type chipset Output Features: • 2 - CPUs @ 2.5V • 13 - SDRAM @ 3.3V • 3 - 3V66 @ 3.3V • 8 - PCI @3.3V • 1 - 24/48MHz@ 3.3V • 1 - 48MHz @ 3.3V fixed • 1 - REF @3.3V, 14.318MHz Features/Benefits: • Programmable output frequency. • Programmable output divider ratios. • Programmable output rise/fall time. • Programmable output skew. • Programmable spread percentage for EMI control. • Watchdog timer technology to reset system if system malfunctions. • Programmable watch dog safe frequency. • Support I 2C Index read/write and block read/write operations. • Uses external 14.318MHz crystal. Key Specifications: • CPU Output Jitter: <250ps • IOAPIC Output Jitter: <500ps • 48MHz, 3V66, PCI Output Jitter: <500ps • Ref Output Jitter. <1000ps • CPU Output Skew: <175ps • PCI Output Skew: <500ps • 3V66 Output Skew <175ps • For group skew timing, please refer to the Group Timing Relationship Table. Programmable Timing Control Hub™ for PII/III™ 1. These pins will have 1.5 to 2X drive strength. * Internal Pull-up resistor of 120K to VDD 56-Pin 300-mil SSOP VDDREF X1 X2 GND GND 3V66_0 3V66_1 3V66_2 VDD3V66 VDDPCI *FS0/PCICLK0 *FS1/PCICLK1 *SEL24_48#/PCICLK2 GND PCICLK3 PCICLK4 PCICLK5 VDDPCI PCICLK6 PCICLK7 GND Vtt_PWRGD/PD# SCLK SDATA VDDSDR SDRAM11 SDRAM10 GND 1 1 1 REF0/FS4 * VDDLAPIC IOAPIC VDDLCPU CPUCLK0 CPUCLK1 GND GND SDRAM0 SDRAM1 SDRAM2 VDDSDR SDRAM3 SDRAM4 SDRAM5 GND SDRAM6 SDRAM7 SDRAM_F VDDSDR GND 24_48MHz/FS2* 48MHZ/FS3* VDD48 VDDSDR SDRAM8 SDRAM9 GND 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 PLL2 PLL1 Spread Spectrum 48MHz 24_48MHz CPUCLK (1:0) 2 12 8 3 SDRAM (11:0) IOAPIC PCICLK (7:0) SDRAM_F 3V66 (2:0) X1 X2 XTAL OSC CPU DIVDER SDRAM DIVDER IOAPIC DIVDER PCI DIVDER 3V66 DIVDER FS(4:0) PD# SEL24_48# Vtt_PWRGD SDATA SCLK Control Logic Config. Reg. / 2 REF0 |
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