SMX320C6413ZTS500 datasheet(21/140 Pages) TI

Part #	SMX320C6413ZTS500

Description	Fixed-Point Digital Signal Processors

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Memory Map Summary

21

April 2004 − Revised May 2005

SPRS247E

2.5.1

L2 Architecture Expanded

Figure 2−4 and Figure 2−5 show the detail of the L2 architecture on the TMS320C6413 and TMS320C6410

devices, respectively . For more information on the L2MODE bits, see the cache configuration (CCFG) register

bit field descriptions in the TMS320C64x Two-Level Internal Memory Reference Guide (literature number

SPRU610).

0x0000 0000

011

010

001

111

0x0002 0000

000

L2MODE

L2 Memory

Block Base Address

0x0003 8000

0x0003 0000

0x0004 0000

128K-Byte SRAM

64K-Byte RAM

32K-Byte RAM

0x0003 FFFF

32K-Byte RAM

Figure 2−4. TMS320C6413 L2 Architecture Memory Configuration

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