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COP8-SW-COP8CW Datasheet(PDF) 3 Page - National Semiconductor (TI) |
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COP8-SW-COP8CW Datasheet(HTML) 3 Page - National Semiconductor (TI) |
3 / 83 page Table of Contents 1.0 General Description ..................................................................................................................................... 1 2.0 Features ....................................................................................................................................................... 1 3.0 Block Diagram .............................................................................................................................................. 2 4.0 Ordering Information .................................................................................................................................... 2 5.0 Connection Diagram .................................................................................................................................... 6 6.0 Architectural Overview ................................................................................................................................. 8 6.1 EMI REDUCTION ...................................................................................................................................... 8 6.2 IN-SYSTEM PROGRAMMING AND VIRTUAL EEPROM ........................................................................ 8 6.3 DUAL CLOCK AND CLOCK DOUBLER ................................................................................................... 8 6.4 TRUE IN-SYSTEM EMULATION .............................................................................................................. 8 6.5 ARCHITECTURE ..................................................................................................................................... 8 6.6 INSTRUCTION SET ................................................................................................................................. 8 6.6.1 Key Instruction Set Features ............................................................................................................... 8 6.6.2 Single Byte/Single Cycle Code Execution ......................................................................................... 8 6.6.3 Many Single-Byte, Multi-Function Instructions .................................................................................... 8 6.6.4 Bit-Level Control .................................................................................................................................. 9 6.6.5 Register Set ......................................................................................................................................... 9 6.7 PACKAGING/PIN EFFICIENCY ................................................................................................................ 9 7.0 Absolute Maximum Ratings ....................................................................................................................... 10 8.0 Electrical Characteristics ............................................................................................................................ 10 9.0 Pin Descriptions ......................................................................................................................................... 15 9.1 EMULATION CONNECTION ................................................................................................................... 16 10.0 Functional Description .............................................................................................................................. 16 10.1 CPU REGISTERS ................................................................................................................................. 16 10.2 PROGRAM MEMORY ........................................................................................................................... 17 10.3 DATA MEMORY .................................................................................................................................... 17 10.4 DATA MEMORY SEGMENT RAM EXTENSION .................................................................................. 17 10.4.1 Virtual EEPROM .............................................................................................................................. 18 10.5 OPTION REGISTER ............................................................................................................................. 18 10.6 SECURITY ............................................................................................................................................ 19 10.7 RESET ................................................................................................................................................... 19 10.7.1 External Reset ................................................................................................................................. 20 10.7.2 On-Chip Brownout Reset ................................................................................................................. 20 10.8 OSCILLATOR CIRCUITS ...................................................................................................................... 21 10.8.1 Oscillator .......................................................................................................................................... 21 10.8.2 Clock Doubler .................................................................................................................................. 22 10.9 CONTROL REGISTERS ....................................................................................................................... 22 10.9.1 CNTRL Register (Address X'00EE) ................................................................................................. 22 10.9.2 PSW Register (Address X'00EF) ..................................................................................................... 22 10.9.3 ICNTRL Register (Address X'00E8) ................................................................................................ 23 10.9.4 T2CNTRL Register (Address X'00C6) ............................................................................................. 23 10.9.5 T3CNTRL Register (Address X'00B6) ............................................................................................. 23 10.9.6 HSTCR Register (Address X'00AF) ................................................................................................ 23 10.9.7 ITMR Register (Address X'00CF) .................................................................................................... 23 10.9.8 ENAD Register (Address X'00CB) .................................................................................................. 23 11.0 In-System Programming ........................................................................................................................... 24 11.1 INTRODUCTION ................................................................................................................................... 24 11.2 FUNCTIONAL DESCRIPTION .............................................................................................................. 24 11.3 REGISTERS .......................................................................................................................................... 24 11.3.1 ISP Address Registers ..................................................................................................................... 24 11.3.2 ISP Read Data Register .................................................................................................................. 24 11.3.3 ISP Write Data Register ................................................................................................................... 24 11.3.4 ISP Write Timing Register ................................................................................................................ 25 11.4 MANEUVERING BACK AND FORTH BETWEEN FLASH MEMORY AND BOOT ROM ..................... 25 11.5 FORCED EXECUTION FROM BOOT ROM ......................................................................................... 26 11.6 RETURN TO FLASH MEMORY WITHOUT HARDWARE RESET ....................................................... 26 11.7 MICROWIRE/PLUS ISP ........................................................................................................................ 26 11.8 USER ISP AND VIRTUAL E 2 ................................................................................................................ 27 11.9 RESTRICTIONS ON SOFTWARE WHEN CALLING ISP ROUTINES IN BOOT ROM ....................... 29 11.10 FLASH MEMORY DURABILITY CONSIDERATIONS ........................................................................ 29 12.0 Timers ....................................................................................................................................................... 30 12.1 TIMER T0 (IDLE TIMER) ...................................................................................................................... 30 www.national.com 3 |
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