CY2220
Document #: 38-07206 Rev. *A
Page 5 of 11
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Switching Characteristics[4] Over the Operating Range
Parameter
Output
Description
Test Conditions
Min.
Max.
Unit
t1
All
Output Duty Cycle[5]
t1A/(t1B)
45
55
%
t2
CPU
Rise Time
Measured at 20% to 80% of VOH
175
700
ps
t2
USB, REF
Rising Edge Rate
Between 0.4V and 2.4V
0.5
2.0
V/ns
t2
PCI, 3V66,
MemRef
Rising Edge Rate
Between 0.4V and 2.4V
1.0
4.0
V/ns
t3
CPU
Fall Time
Measured at 80% to 20% of VOH
175
700
ps
t3
USB, REF
Falling Edge Rate
Between 2.4V and 0.4V
0.5
2.0
V/ns
t3
PCI, 3V66,
MemRef
Falling Edge Rate
Between 2.4V and 0.4V
1.0
4.0
V/ns
t4
CPU
CPU-CPU Skew
Measured at Crossover
150
ps
t5
3V66
3V66-3V66 Skew
Measured at 1.5V
250
ps
t6
PCI
PCI-PCI Skew
Measured at 1.5V
500
ps
t7
3V66,PCI
3V66-PCI Clock Skew
3V66 leads. Measured at 1.5V
1.5
3.5
ns
t8
CPU
Cycle-Cycle Clock Jitter
Measured at Crossover t8 = t8A – t8B
With all outputs running
200
ps
t9
Mref
Cycle-Cycle Clock Jitter
Measured at 1.5V t9 = t9A – t9B
250
ps
t9
3V66
Cycle-Cycle Clock Jitter
Measured at 1.5V t9 = t9A – t9B
300
ps
t9
USB
Cycle-Cycle Clock Jitter
Measured at 1.5V t9 = t9A – t9B
350
ps
t9
PCI
Cycle-Cycle Clock Jitter
Measured at 1.5V t9 = t9A – t9B
500
ps
t9
REF
Cycle-Cycle Clock Jitter
Measured at 1.5V t9 = t9A – t9B
1000
ps
CPU, PCI
Settle Time
CPU and PCI clock stabilization from
power-up
3
ms
CPU
Rise/Fall Matching
Measured with test loads[6, 7]
20%
CPU
Overshoot
Measured with test loads[7]
VOH +
0.2
V
CPU
Undershoot
Measured with test loads[7]
–0.2
V
Voh
CPU
High-level Output Voltage
Measured with test loads[7]
0.65
0.74
V
Vol
CPU
Low-level Output Voltage
Measured with test loads[7]
0.0
0.05
V
Vcrossover
CPU
Crossover Voltage
Measured with test loads[7]
45%
of
VOH
55%
of
VOH
V
Notes:
4.
All parameters specified with loaded outputs. Parameters not tested in production, but are guaranteed by design characterization.
5.
Duty cycle is measured at 1.5V with VDD at 3.3V on all output except CPU. Duty Cycle on CPU is measured at VCrossover.
6.
Determined as a fraction of 2*(tRP – tRN)/(tRP + tRN)Where tRP is a rising edge and tRN is an intersecting falling edge.
7.
The test load is specified in test circuit.
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