Electronic Components Datasheet Search |
|
M368L1624DTL-CLB3 Datasheet(PDF) 9 Page - Samsung semiconductor |
|
M368L1624DTL-CLB3 Datasheet(HTML) 9 Page - Samsung semiconductor |
9 / 12 page 184pin Unbuffered DDR SDRAM MODULE M368L1624DTL Rev. 0.1 May. 2002 1. Maximum burst refresh cycle : 8 2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. 3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly. 4. A write command can be applied with tRCD satisfied after this command. 5. For registered DIMMs, tCL and tCH are ≥ 45% of the period including both the half period jitter (t JIT(HP)) of the PLL and the half period jitter due to crosstalk (tJIT(crosstalk) ) on the DIMM. 6. Input Setup/Hold Slew Rate Derating This derating table is used to increase tIS/tIH in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. 7. I/O Setup/Hold Slew Rate Derating This derating table is used to increase tDS/tDH in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. Parameter Symbol -TCB3 (DDR333) -TCA2 (DDR266A) -TCB0 (DDR266B) Unit Note Min Max Min Max Min Max Mode register set cycle time tMRD 12 15 15 ns DQ & DM setup time to DQS tDS 0.45 0.5 0.5 ns 7,8,9 DQ & DM hold time to DQS tDH 0.45 0.5 0.5 ns 7,8,9 Control & Address input pulse width tIPW 2.2 2.2 2.2 ns DQ & DM input pulse width tDIPW 1.75 1.75 1.75 ns Power down exit time tPDEX 6 7.5 7.5 ns Exit self refresh to non-Read command tXSNR 75 75 75 ns 4 Exit self refresh to read command tXSRD 200 200 200 tCK Refresh interval time tREFI 7.8 7.8 7.8 us 1 Output DQS valid window tQH tHP -tQHS - tHP -tQHS - tHP -tQHS - ns 5 Clock half period tHP tCLmin or tCHmin - tCLmin or tCHmin - tCLmin or tCHmin - ns Data hold skew factor tQHS 0.55 0.75 0.75 ns DQS write postamble time tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK 3 Active to Read with Auto precharge command tRAP 20 20 20 Autoprecharge write recovery + Precharge time tDAL (tWR/tCK) + (tRP/tCK) (tWR/tCK) + (tRP/tCK) (tWR/tCK) + (tRP/tCK) tCK 11 Input Setup/Hold Slew Rate ∆tIS ∆tIH (V/ns) (ps) (ps) 0.5 0 0 0.4 +50 +50 0.3 +100 +100 I/O Setup/Hold Slew Rate ∆tDS ∆tDH (V/ns) (ps) (ps) 0.5 0 0 0.4 +75 +75 0.3 +150 +150 |
Similar Part No. - M368L1624DTL-CLB3 |
|
Similar Description - M368L1624DTL-CLB3 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |