184pin Unbuffered DDR SDRAM MODULE

M368L1624DTL

Rev. 0.1 May. 2002

DDR SDRAM module IDD spec table

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

Symbol

B3(DDR333@CL=2.5)

A2(DDR266@CL=2)

B0(DDR266@CL=2.5)

Unit

Notes

IDD0

360

320

320

mA

IDD1

500

460

460

mA

IDD2P

12

12

12

mA

IDD2F

100

80

80

mA

IDD2Q

80

72

72

mA

IDD3P

140

120

120

mA

IDD3N

220

180

180

mA

IDD4R

800

680

680

mA

IDD4W

760

620

620

mA

IDD5

720

660

660

mA

IDD6

Normal

12

12

12

mA

Low power

6

6

6

mA

Optional

IDD7A

1400

1200

1200

mA

AC Operating Conditions

Parameter/Condition

Symbol

Min

Max

Unit

Note

Input High (Logic 1) Voltage, DQ, DQS and DM signals

VIH(AC)

VREF + 0.31

V

3

Input Low (Logic 0) Voltage, DQ, DQS and DM signals.

VIL(AC)

VREF - 0.31

V

3

Input Differential Voltage, CK and CK inputs

VID(AC)

0.7

VDDQ+0.6

V

1

Input Crossing Point Voltage, CK and CK inputs

VIX(AC)

0.5*VDDQ-0.2

0.5*VDDQ+0.2

V

2

Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK.

3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simula-

tion. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.

Parameter

Value

Unit

Note

Input reference voltage for Clock

V

Input signal maximum peak swing

1.5

V

V

Input timing measurement reference level

V

Output timing measurement reference level

V

Output load condition

See Load Circuit