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DS3112 Datasheet(PDF) 6 Page - Dallas Semiconductor |
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DS3112 Datasheet(HTML) 6 Page - Dallas Semiconductor |
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6 / 135 page  DS3112 6 of 135 MAIN DS3112 TEMPE FEATURES Table 1B General Features § Can be operated as a standalone T3 or E3 framer without any M13 or E13 multiplexing § T1/E1 FIFOs in the receive direction provide T1/E1 demultiplexed clocks with very little jitter § Two T1/E1 drop and insert ports § B3ZS/HDB3 encoder and decoder § T3 C-Bit Parity mode § All the receive T1/E1 ports can be clocked out on a common clock § All the transmit T1/E1 ports can be clocked in on a common clock § Generates gapped clocks that can be used as demand clocks in unchannelized T3/E3 applications § T1/E1 ports can be configured into a “loop-timed” mode § T3/E3 port interfaces can be either bipolar or unipolar § The clock, data, and control signals can be inverted to allow a glueless interface to other device § Loss of transmit and receive clock detect T3/E3 Framer § Generates T3/E3 Alarm Indication Signal (AIS) and Remote Alarm Indication (RAI) alarms § Transmit framer pass through mode § Generates T3 idle signal § Detects the following T3/E3 alarms and events: Loss Of Signal (LOS), Loss Of Frame (LOF), Alarm Indication Signal (AIS), Remote Alarm Indication (RAI), T3 idle signal, Change Of Frame Alignment (COFA), B3ZS and HDB3 code words being received, Severely Errored Framing Event (SEFE), and T3 Application ID status indication T2/E2 Framer § Generates T2/E2 Alarm Indication Signal (AIS) and Remote Alarm Indication (RAI) alarms § Generates Alarm Indication Signal (AIS) for T1/E1 data streams in both the transmit and receive directions § Detects the following T2/E2 alarms and events: Loss Of Frame (LOF), Alarm Indication Signal (AIS), and Remote Alarm Indication (RAI) § Detects T1 line loopback commands (C3 bit is the inverse of C1 and C2) § Generates T1 line loopback commands HDLC Controller § Designed to handle multiple LAPD messages without Host intervention § 256 byte receive and transmit buffers are large enough to handle the three T3 messages (Path ID, Idle Signal ID, and Test Signal ID) that are sent and received once a second which means the Host only needs to access the HDLC Controller once a second § Handles all of the normal Layer 2 tasks such as zero stuffing/destuffing, CRC generation/checking, abort generation/checking, flag generation/detection, and byte alignment § Programmable high and low watermarks for the FIFO § HDLC Controller can be used in either the T3 C-Bit Parity Mode or in the Sn Bits in the E3 Mode |
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