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MT49H32M9CFM-XX Datasheet(PDF) 1 Page - Micron Technology |
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MT49H32M9CFM-XX Datasheet(HTML) 1 Page - Micron Technology |
1 / 44 page PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. pdf: 09005aef80a41b59/zip: 09005aef811ba111 MT49H8M18C_1.fm - Rev. F 11/04 EN 1 ©2004 Micron Technology, Inc. All rights reserved. 16 MEG x 18, 32 MEG x 9 2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II 288Mb SIO REDUCED LATENCY (RLDRAM II) MT49H16M18C MT49H32M9C Features • 288Mb • 400 MHz DDR operation (800 Mb/s/pin data rate) • Organization • 16 Meg x 18, 32 Meg x 9 Separate I/O •8 banks • Cyclic bank switching for maximum bandwidth • Reduced cycle time (20ns at 400 MHz) • Nonmultiplexed addresses (address multiplexing option available) • SRAM-type interface • Read latency (RL), row cycle time, and burst sequence length • Balanced READ and WRITE latencies in order to optimize data bus utilization • Data mask for WRITE commands • Differential input clocks (CK, CK#) • Differential input data clocks (DKx, DKx#) • On-chip DLL generates CK edge-aligned data and output data clock signals • Data valid signal (QVLD) • 32ms refresh (8K refresh for each bank; 64k refresh command must be issued in total each 32ms) • 144-ball FBGA package • HSTL I/O (1.5V or 1.8V nominal) •25Ω–60Ω matched impedance outputs • 2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O • On-die termination (ODT) RTT NOTE: 1. Contact Micron for availability of lead-free products. Options Marking • Clock Cycle Timing 2.5ns (400 MHz) 3.3ns (300 MHz) 5ns (200 MHz) -25 -33 -5 •Configuration 16 Meg x 18 32 Meg x 9 MT49H16M18CFM MT49H32M9CFM •Package 144-ball FBGA (11mm x 18.5mm) FM BM (lead-free)1 Table 1: Valid Part Numbers PART NUMBER DESCRIPTION MT49H16M18CFM-xx 16 Meg x 18 RLDRAM II MT49H32M9CFM-xx 32 Meg x 9 RLDRAM II Figure 1: 144-Ball FBGA |
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