Contents
CY8C22xxx Preliminary Data Sheet
8
Document No. 38-12009 Rev. *D
December 22, 2003
17. Digital Blocks ....................................................................................................... 189
17.1
Architectural Description ....................................................................................................189
17.1.1
Input Multiplexers......................................................................................... 189
17.1.2
Input Clock Resynchronization .................................................................... 190
17.1.3
Output De-Multiplexers ................................................................................191
17.1.4
Block Chaining Signals ................................................................................191
17.1.5
Timer Function .............................................................................................192
17.1.6
Counter Function ......................................................................................... 192
17.1.7
Dead Band Function .................................................................................... 193
17.1.8
CRCPRS Function .......................................................................................194
17.1.9
SPI Protocol Function .................................................................................. 195
17.1.10
SPI Master Function .................................................................................... 196
17.1.11
SPI Slave Function ...................................................................................... 196
17.1.12
Asynchronous Transmitter Function ............................................................ 197
17.1.13
Asynchronous Receiver Function ................................................................ 197
17.2
Register Definitions............................................................................................................ 198
17.2.1
DxBxxDRx Registers ................................................................................... 198
17.2.2
DxBxxCR0 Register ..................................................................................... 203
17.2.3
INT_MSK1 Register ..................................................................................... 203
17.2.4
DxBxxFN Registers...................................................................................... 203
17.2.5
DxBxxIN Registers.......................................................................................204
17.2.6
DxBxxOU Registers ..................................................................................... 204
17.3
Timing Diagrams................................................................................................................ 204
17.3.1
Timer Timing ................................................................................................ 205
17.3.2
Counter Timing ............................................................................................ 206
17.3.3
Dead Band Timing .......................................................................................206
17.3.4
CRCPRS Timing .......................................................................................... 208
17.3.5
SPI Mode Timing ......................................................................................... 208
17.3.6
SPIM Timing ................................................................................................ 209
17.3.7
SPIS Timing ................................................................................................. 212
17.3.8
Transmitter Timing .......................................................................................215
17.3.9
Receiver Timing ........................................................................................... 216
SECTION E ANALOG SYSTEM
219
Top-Level Analog Architecture ...................................................................................................... 219
Analog Register Summary ............................................................................................................. 221
18. Analog Interface ................................................................................................... 223
18.1
Architectural Description ....................................................................................................223
18.1.1
Analog Data Bus Interface ........................................................................... 223
18.1.2
Analog Comparator Bus Interface................................................................ 223
18.1.3
Analog Column Clock Generation................................................................ 225
18.1.4
Decimator and Incremental ADC Interface .................................................. 226
18.1.5
Analog Modulator Interface (Mod Bits) ........................................................ 226
18.1.6
Analog Synchronization Interface (Stalling) ................................................. 226
18.1.7
SAR Hardware Acceleration ........................................................................ 226
18.2
Register Definitions............................................................................................................ 228
18.2.1
CMP_CR0 Register ..................................................................................... 228
18.2.2
CMP_CR1 Register ..................................................................................... 228
18.2.3
ASY_CR Register ........................................................................................ 228
18.2.4
DEC_CR0 Register...................................................................................... 229
18.2.5
DEC_CR1 Register...................................................................................... 229
18.2.6
CLK_CR0 Register ...................................................................................... 230
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