December 22, 2003
Document No. 38-12009 Rev. *D
7
CY8C22xxx Preliminary Data Sheet
Contents
13.1.58
CPU_SCR0 .................................................................................................144
13.2
Bank 1 Registers................................................................................................................145
13.2.1
PRTxDM0 ....................................................................................................145
13.2.2
PRTxDM1 ....................................................................................................146
13.2.3
PRTxIC0 ......................................................................................................147
13.2.4
PRTxIC1 ......................................................................................................148
13.2.5
DxBxxFN .....................................................................................................149
13.2.6
DxBxxIN ......................................................................................................151
13.2.7
DxBxxOU ....................................................................................................152
13.2.8
CLK_CR0 ....................................................................................................154
13.2.9
CLK_CR1 ....................................................................................................155
13.2.10
ABF_CR0 ....................................................................................................156
13.2.11
AMD_CR1 .................................................................................................157
13.2.12
ALT_CR0 ....................................................................................................158
13.2.13
GDI_O_IN ...................................................................................................159
13.2.14
GDI_E_IN ....................................................................................................160
13.2.15
GDI_O_OU ..................................................................................................161
13.2.16
GDI_E_OU ..................................................................................................162
13.2.17
OSC_CR4 ...................................................................................................163
13.2.18
OSC_CR3 ...................................................................................................164
13.2.19
OSC_CR0 ...................................................................................................165
13.2.20
OSC_CR1 ...................................................................................................166
13.2.21
OSC_CR2 ...................................................................................................167
13.2.22
VLT_CR ......................................................................................................168
13.2.23
VLT_CMP ....................................................................................................169
13.2.24
IMO_TR .......................................................................................................170
13.2.25
ILO_TR ........................................................................................................171
13.2.26
BDG_TR ......................................................................................................172
13.2.27
ECO_TR ......................................................................................................173
SECTION D DIGITAL SYSTEM
175
Top-Level Digital Architecture ........................................................................................................175
Digital Register Summary ..............................................................................................................176
14. Global Digital Interconnect (GDI) .......................................................................... 177
14.1
Architectural Description ....................................................................................................177
14.2
Register Definitions ............................................................................................................179
14.2.1
GDI_O_IN and GDI_E_IN Registers............................................................179
14.2.2
GDI_O_OU and GDI_E_OU Registers ........................................................179
15. Array Digital Interconnect (ADI) ............................................................................ 181
15.1
Architectural Description ....................................................................................................181
16. Row Digital Interconnect (RDI) .............................................................................. 183
16.1
Architectural Description ....................................................................................................183
16.2
Register Definitions ............................................................................................................186
16.2.1
RDIxRI Register ...........................................................................................186
16.2.2
RDIxSYN Register .......................................................................................186
16.2.3
RDIxIS Register ...........................................................................................186
16.2.4
RDIxLTx Registers .......................................................................................187
16.2.5
RDIxROx Registers......................................................................................187
16.3
Timing Diagram .................................................................................................................187
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