UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ

LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR

SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002

9

POST OFFICE BOX 655303

APPLICATION INFORMATION

UCC384 short-circuit timing (continued)

During an overcurrent condition, the regulator actively limits the maximum output current to the peak-current

limit. This limits the output voltage of the regulator to:

V

OUT +

I

PEAK

R

L

(1)

If the output current stays above the overcurrent threshold, the voltage on the SD/CT pin reaches –2.6 V with

respect to GND and the output turns off. The CT capacitor is then discharged by a 1-

µA current source. When

the voltage on the SD/CT pin reaches –1.6 V with respect to GND, the output turns back on. This process repeats

until the output current falls below the overcurrent threshold.

t

ON +

CT (

mF)

1V

40

mA

seconds

(2)

t

OFF +

CT (

mF)

1V

1

mA

seconds

(3)

capacitive loads

A capacitive load on the regulator’s output appears as a short-circuit during start-up. If the capacitance is too

mode operation. For a constant current load the maximum allowed output capacitance is calculated as follows:

C

OUT(max) +

I

PEAK

(A)

* I

LOAD

(A)

t

ON

(sec)

V

OUT

(V)

Farads

(4)

capacitor selected. For a resistive load the maximum output capacitor can be estimated as follows:

C

OUT(max) +

t

ON

(sec)

R

LOAD

(

W)

n

1

V

OUT

(V)

I

MAX

(A)

R

LOAD

(

W)

Farads

(5)

Figure 6 and Figure 7 are oscilloscope photos of the UCC384–ADJ operating during an overcurrent condition.

Figure 6 shows operation of the circuit as the output current initially rises above the overcurrent threshold. This

is shown on a 1ms/div. scale. Figure 7 shows operation of the same circuit on a 25 ms/div. scale showing one

complete cycle of operation during an overcurrent condition.